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-rw-r--r--manual/CHAPTER_StateOfTheArt/arrays01.v16
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diff --git a/manual/CHAPTER_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v
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--- a/manual/CHAPTER_StateOfTheArt/arrays01.v
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-module uut_arrays01(clock, we, addr, wr_data, rd_data);
-
-input clock, we;
-input [3:0] addr, wr_data;
-output [3:0] rd_data;
-reg [3:0] rd_data;
-
-reg [3:0] memory [15:0];
-
-always @(posedge clock) begin
- if (we)
- memory[addr] <= wr_data;
- rd_data <= memory[addr];
-end
-
-endmodule