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-rw-r--r--manual/APPNOTE_010_Verilog_to_BLIF.tex2
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diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex
index 5b1c0c359..0d0d3e5cd 100644
--- a/manual/APPNOTE_010_Verilog_to_BLIF.tex
+++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex
@@ -438,7 +438,7 @@ design to fit a certain need without actually touching the RTL code.
\bibitem{yosys}
Clifford Wolf. The Yosys Open SYnthesis Suite. \\
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
\bibitem{bigsim}
yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\