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-rw-r--r--kernel/rtlil.h2
-rw-r--r--kernel/yosys.cc4
2 files changed, 5 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f4fcf5dcf..82cbfaf28 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1327,7 +1327,7 @@ public:
#endif
};
-struct RTLIL::CaseRule
+struct RTLIL::CaseRule : public RTLIL::AttrObject
{
std::vector<RTLIL::SigSpec> compare;
std::vector<RTLIL::SigSig> actions;
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index f95c0127b..a42a7c0b8 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1273,6 +1273,10 @@ struct ScriptCmdPass : public Pass {
log("If only one label is specified (without ':') then only the block\n");
log("marked with that label (until the next label) is executed.\n");
log("\n");
+ log("In \"-scriptwire\" mode, the commands on the selected wire(s) will be executed\n");
+ log("in the scope of (and thus, relative to) the wires' owning module(s). This\n");
+ log("'-module' mode can be exited by using the 'cd' command.\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{