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-rw-r--r--frontends/verific/verific.cc44
-rw-r--r--frontends/verilog/preproc.cc18
-rw-r--r--frontends/verilog/verilog_frontend.cc16
3 files changed, 66 insertions, 12 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c5eef4b55..a5c4aa26a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -787,7 +787,18 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
{
std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();
- std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name);
+ std::string module_name = netlist_name;
+
+ if (nl->IsOperator()) {
+ module_name = "$verific$" + module_name;
+ } else {
+ if (*nl->Name()) {
+ module_name += "(";
+ module_name += nl->Name();
+ module_name += ")";
+ }
+ module_name = "\\" + module_name;
+ }
netlist = nl;
@@ -1256,7 +1267,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT)
sva_asserts.insert(inst);
- if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME)
+ if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_RESTRICT)
sva_assumes.insert(inst);
if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER)
@@ -1396,8 +1407,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
import_verific_cells:
nl_todo.insert(inst->View());
- RTLIL::Cell *cell = module->addCell(inst_name, inst->IsOperator() ?
- std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name()));
+ std::string inst_type = inst->View()->Owner()->Name();
+
+ if (inst->View()->IsOperator()) {
+ inst_type = "$verific$" + inst_type;
+ } else {
+ if (*inst->View()->Name()) {
+ inst_type += "(";
+ inst_type += inst->View()->Name();
+ inst_type += ")";
+ }
+ inst_type = "\\" + inst_type;
+ }
+
+ RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
if (inst->IsPrimitive() && mode_keep)
cell->attributes["\\keep"] = 1;
@@ -1939,12 +1962,18 @@ struct VerificPass : public Pass {
log("Load the specified VHDL files into Verific.\n");
log("\n");
log("\n");
- log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
+ log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
log("(default library when -work is not present: \"work\")\n");
log("\n");
log("\n");
+ log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
+ log("\n");
+ log("Look up external definitions in the specified library.\n");
+ log("(-L may be used more than once)\n");
+ log("\n");
+ log("\n");
log(" verific -vlog-incdir <directory>..\n");
log("\n");
log("Add Verilog include directories.\n");
@@ -2158,12 +2187,17 @@ struct VerificPass : public Pass {
goto check_error;
}
+ veri_file::RemoveAllLOptions();
for (; argidx < GetSize(args); argidx++)
{
if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
work = args[++argidx];
continue;
}
+ if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
+ veri_file::AddLOption(args[++argidx].c_str());
+ continue;
+ }
break;
}
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index dea22ee8a..7e107dc26 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -490,13 +490,17 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
}
while (newline_count-- > 0)
return_char('\n');
- // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
- defines_map[name] = value;
- if (state == 2)
- defines_with_args.insert(name);
- else
- defines_with_args.erase(name);
- global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2);
+ if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) {
+ // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
+ defines_map[name] = value;
+ if (state == 2)
+ defines_with_args.insert(name);
+ else
+ defines_with_args.erase(name);
+ global_defines_cache[name] = std::pair<std::string, bool>(value, state == 2);
+ } else {
+ log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str());
+ }
continue;
}
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 0e2bead6f..058d750c3 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -553,6 +553,12 @@ struct VerilogDefines : public Pass {
log(" -Uname[=definition]\n");
log(" undefine the preprocessor symbol 'name'\n");
log("\n");
+ log(" -reset\n");
+ log(" clear list of defined preprocessor symbols\n");
+ log("\n");
+ log(" -list\n");
+ log(" list currently defined preprocessor symbols\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -588,6 +594,16 @@ struct VerilogDefines : public Pass {
design->verilog_defines.erase(name);
continue;
}
+ if (arg == "-reset") {
+ design->verilog_defines.clear();
+ continue;
+ }
+ if (arg == "-list") {
+ for (auto &it : design->verilog_defines) {
+ log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str());
+ }
+ continue;
+ }
break;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-11 22:14:23 +0000