diff options
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 7 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
2 files changed, 8 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 78e83e038..6c2eafacd 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1497,6 +1497,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->parameters["\\WIDTH"] = width; + if (attributes.count("\\reg")) { + auto &attr = attributes.at("\\reg"); + if (attr->type != AST_CONSTANT) + log_error("Attribute `reg' with non-constant value at %s:%d!\n", filename.c_str(), linenum); + cell->attributes["\\reg"] = attr->asAttrConst(); + } + Wire *wire = current_module->addWire(myid + "_wire", width); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->setPort("\\Y", wire); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 154b59ebc..c5ff3d402 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -764,6 +764,7 @@ wire_name_and_opt_assign: AstNode *fcall = new AstNode(AST_FCALL); wire->str = ast_stack.back()->children.back()->str; fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq"; + fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall)); } } | |