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-rw-r--r--frontends/verilog/verilog_lexer.l8
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 4acfb414d..ca23df3e8 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -28,7 +28,7 @@
*
* A simple lexer for Verilog code. Non-preprocessor compiler directives are
* handled here. The preprocessor stuff is handled in preproc.cc. Everything
- * else is left to the bison parser (see parser.y).
+ * else is left to the bison parser (see verilog_parser.y).
*
*/
@@ -188,9 +188,9 @@ YOSYS_NAMESPACE_END
"unique0" { SV_KEYWORD(TOK_UNIQUE); }
"priority" { SV_KEYWORD(TOK_PRIORITY); }
-"always_comb" { SV_KEYWORD(TOK_ALWAYS); }
-"always_ff" { SV_KEYWORD(TOK_ALWAYS); }
-"always_latch" { SV_KEYWORD(TOK_ALWAYS); }
+"always_comb" { SV_KEYWORD(TOK_ALWAYS_COMB); }
+"always_ff" { SV_KEYWORD(TOK_ALWAYS_FF); }
+"always_latch" { SV_KEYWORD(TOK_ALWAYS_LATCH); }
/* use special token for labels on assert, assume, cover, and restrict because it's insanley complex
to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some