diff options
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 50c2a3ce6..32fbddd65 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -117,7 +117,7 @@ struct ConstEvalAig sig2deps[output].insert(output); RTLIL::Cell *cell = sig2driver.at(output); - RTLIL::SigBit sig_a = cell->getPort("\\A"); + RTLIL::SigBit sig_a = cell->getPort(ID::A); sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -126,7 +126,7 @@ struct ConstEvalAig compute_deps(sig_a, inputs); if (cell->type == "$_AND_") { - RTLIL::SigSpec sig_b = cell->getPort("\\B"); + RTLIL::SigSpec sig_b = cell->getPort(ID::B); sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation // that may occur does so here, and // not mid insertion (below) @@ -142,11 +142,11 @@ struct ConstEvalAig bool eval(RTLIL::Cell *cell) { - RTLIL::SigBit sig_y = cell->getPort("\\Y"); + RTLIL::SigBit sig_y = cell->getPort(ID::Y); if (values_map.count(sig_y)) return true; - RTLIL::SigBit sig_a = cell->getPort("\\A"); + RTLIL::SigBit sig_a = cell->getPort(ID::A); if (!eval(sig_a)) return false; @@ -162,7 +162,7 @@ struct ConstEvalAig } { - RTLIL::SigBit sig_b = cell->getPort("\\B"); + RTLIL::SigBit sig_b = cell->getPort(ID::B); if (!eval(sig_b)) return false; if (sig_b == State::S0) { @@ -930,7 +930,7 @@ void AigerReader::post_process() for (auto cell : module->cells().to_vector()) { if (cell->type != "$lut") continue; - auto y_port = cell->getPort("\\Y").as_bit(); + auto y_port = cell->getPort(ID::Y).as_bit(); if (y_port.wire->width == 1) module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str())); else |