diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 47 |
1 files changed, 28 insertions, 19 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 359d951b9..d934a9aa9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -93,7 +93,6 @@ struct XAigerWriter dict<SigBit, int> ordered_outputs; vector<Cell*> box_list; - dict<IdString, std::vector<IdString>> box_ports; int mkgate(int a0, int a1) { @@ -296,6 +295,7 @@ struct XAigerWriter //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } + dict<IdString, std::vector<IdString>> box_ports; for (auto cell : box_list) { log_assert(cell); @@ -405,7 +405,8 @@ struct XAigerWriter if (holes_mode) { struct sort_by_port_id { bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const { - return a.wire->port_id < b.wire->port_id; + return a.wire->port_id < b.wire->port_id || + (a.wire->port_id == b.wire->port_id && a.offset < b.offset); } }; input_bits.sort(sort_by_port_id()); @@ -545,7 +546,7 @@ struct XAigerWriter RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); log_assert(holes_module); - dict<IdString, Cell*> cell_cache; + dict<IdString, std::tuple<int,int,int>> cell_cache; int box_count = 0; for (auto cell : box_list) { @@ -554,24 +555,32 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - int box_inputs = 0, box_outputs = 0; - for (auto port_name : box_module->ports) { - RTLIL::Wire *w = box_module->wire(port_name); - log_assert(w); - if (w->port_input) - box_inputs += GetSize(w); - if (w->port_output) - box_outputs += GetSize(w); - } + auto r = cell_cache.insert(cell->type); + auto &v = r.first->second; + if (r.second) { + int box_inputs = 0, box_outputs = 0; + for (auto port_name : box_module->ports) { + RTLIL::Wire *w = box_module->wire(port_name); + log_assert(w); + if (w->port_input) + box_inputs += GetSize(w); + if (w->port_output) + box_outputs += GetSize(w); + } - // For flops only, create an extra 1-bit input that drives a new wire - // called "<cell>.abc9_ff.Q" that is used below - if (box_module->get_bool_attribute("\\abc9_flop")) - box_inputs++; + // For flops only, create an extra 1-bit input that drives a new wire + // called "<cell>.abc9_ff.Q" that is used below + if (box_module->get_bool_attribute("\\abc9_flop")) + box_inputs++; + + std::get<0>(v) = box_inputs; + std::get<1>(v) = box_outputs; + std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int(); + } - write_h_buffer(box_inputs); - write_h_buffer(box_outputs); - write_h_buffer(box_module->attributes.at("\\abc9_box_id").as_int()); + write_h_buffer(std::get<0>(v)); + write_h_buffer(std::get<1>(v)); + write_h_buffer(std::get<2>(v)); write_h_buffer(box_count++); } |