diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/aiger.cc | 3 | ||||
| -rw-r--r-- | backends/smt2/smtio.py | 15 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 9 |
3 files changed, 17 insertions, 10 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 3e8b14dee..44718baae 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -91,6 +91,9 @@ struct AigerWriter } else if (alias_map.count(bit)) { a = bit2aig(alias_map.at(bit)); + } else + if (initstate_bits.count(bit)) { + a = initstate_ff; } if (bit == State::Sx || bit == State::Sz) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index bac68ac70..1df996aa7 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -1032,12 +1032,17 @@ class MkVcd: print("$var integer 32 t smt_step $end", file=self.f) print("$var event 1 ! smt_clock $end", file=self.f) + def vcdescape(n): + if n.startswith("$") or ":" in n: + return "\\" + n + return n + scope = [] for path in sorted(self.nets): key, width = self.nets[path] uipath = list(path) - if "." in uipath[-1]: + if "." in uipath[-1] and not uipath[-1].startswith("$"): uipath = uipath[0:-1] + uipath[-1].split(".") for i in range(len(uipath)): uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i]) @@ -1048,15 +1053,13 @@ class MkVcd: while uipath[:-1] != scope: scopename = uipath[len(scope)] - if scopename.startswith("$"): - scopename = "\\" + scopename - print("$scope module %s $end" % scopename, file=self.f) + print("$scope module %s $end" % vcdescape(scopename), file=self.f) scope.append(uipath[len(scope)]) if path in self.clocks and self.clocks[path][1] == "event": - print("$var event 1 %s %s $end" % (key, uipath[-1]), file=self.f) + print("$var event 1 %s %s $end" % (key, vcdescape(uipath[-1])), file=self.f) else: - print("$var wire %d %s %s $end" % (width, key, uipath[-1]), file=self.f) + print("$var wire %d %s %s $end" % (width, key, vcdescape(uipath[-1])), file=self.f) for i in range(len(scope)): print("$upscope $end", file=self.f) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 7b1db4776..24e397bda 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -371,13 +371,14 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) } } -void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool as_comment = false) +void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool regattr = false, bool as_comment = false) { if (noattr) return; if (attr2comment) as_comment = true; for (auto it = attributes.begin(); it != attributes.end(); ++it) { + if (it->first == "\\init" && regattr) continue; f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); if (modattr && (it->second == State::S0 || it->second == Const(0))) @@ -392,7 +393,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) { - dump_attributes(f, indent, wire->attributes); + dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); #if 0 if (wire->port_input && !wire->port_output) f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); @@ -1521,7 +1522,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { - dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true); + dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { if (got_default) continue; @@ -1686,7 +1687,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } } - dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true); + dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { |