diff options
Diffstat (limited to 'backends')
-rw-r--r-- | backends/blif/blif.cc | 4 | ||||
-rw-r--r-- | backends/edif/edif.cc | 4 | ||||
-rw-r--r-- | backends/json/json.cc | 8 | ||||
-rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
4 files changed, 10 insertions, 9 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index ba29d9090..23d1d58fc 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -512,8 +512,8 @@ struct BlifBackend : public Backend { log(" suppresses the generation of this nets without fanout.\n"); log("\n"); log("The following options can be useful when the generated file is not going to be\n"); - log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n"); - log("file *.blif when any of this options is used.\n"); + log("read by a BLIF parser but a custom tool. It is recommended to not name the\n"); + log("output file *.blif when any of this options is used.\n"); log("\n"); log(" -icells\n"); log(" do not translate Yosys's internal gates to generic BLIF logic\n"); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 370108444..7722d0c33 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -107,8 +107,8 @@ struct EdifBackend : public Backend { log(" constant drivers first)\n"); log("\n"); log(" -gndvccy\n"); - log(" create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is \"G\"\n"); - log(" for \"GND\" and \"P\" for \"VCC\".)\n"); + log(" create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is\n"); + log(" \"G\" for \"GND\" and \"P\" for \"VCC\".)\n"); log("\n"); log(" -attrprop\n"); log(" create EDIF properties for cell attributes\n"); diff --git a/backends/json/json.cc b/backends/json/json.cc index 270d762ee..1ff0a6c66 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -397,8 +397,8 @@ struct JsonBackend : public Backend { log(" \"signed\": <1 if the port is signed>\n"); log(" }\n"); log("\n"); - log("The \"offset\" and \"upto\" fields are skipped if their value would be 0."); - log("They don't affect connection semantics, and are only used to preserve original"); + log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.\n"); + log("They don't affect connection semantics, and are only used to preserve original\n"); log("HDL bit indexing."); log("And <cell_details> is:\n"); log("\n"); @@ -459,8 +459,8 @@ struct JsonBackend : public Backend { log("connected to a constant driver are denoted as string \"0\", \"1\", \"x\", or\n"); log("\"z\" instead of a number.\n"); log("\n"); - log("Bit vectors (including integers) are written as string holding the binary"); - log("representation of the value. Strings are written as strings, with an appended"); + log("Bit vectors (including integers) are written as string holding the binary\n"); + log("representation of the value. Strings are written as strings, with an appended\n"); log("blank in cases of strings of the form /[01xz]* */.\n"); log("\n"); log("For example the following Verilog code:\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index aa1d4558c..e60ebc70e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2160,7 +2160,8 @@ struct VerilogBackend : public Backend { log(" as binary numbers.\n"); log("\n"); log(" -simple-lhs\n"); - log(" Connection assignments with simple left hand side without concatenations.\n"); + log(" Connection assignments with simple left hand side without\n"); + log(" concatenations.\n"); log("\n"); log(" -extmem\n"); log(" instead of initializing memories using assignments to individual\n"); |