diff options
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
-rw-r--r-- | backends/verilog/verilog_backend.cc | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index d3b5d52db..aa2f88fa4 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -293,17 +293,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_ { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { fprintf(f, "$signed("); - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); fprintf(f, ")"); } else - dump_sigspec(f, cell->connections_["\\" + port]); + dump_sigspec(f, cell->connections()["\\" + port]); } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections_.count("\\Q") > 0) + if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0) { - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (SIZE(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; @@ -338,7 +338,7 @@ no_special_reg_name: void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s ", op.c_str()); dump_attributes(f, "", cell->attributes, ' '); dump_cell_expr_port(f, cell, "A", true); @@ -348,7 +348,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", true); fprintf(f, " %s ", op.c_str()); @@ -361,7 +361,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { if (cell->type == "$_INV_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); fprintf(f, "~"); dump_attributes(f, "", cell->attributes, ' '); @@ -372,7 +372,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "A", false); fprintf(f, " "); @@ -391,7 +391,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$_MUX_") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); dump_cell_expr_port(f, cell, "S", false); fprintf(f, " ? "); @@ -406,23 +406,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type.substr(0, 6) == "$_DFF_") { std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); if (cell->type[7] != '_') { fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); } fprintf(f, ")\n"); if (cell->type[7] != '_') { fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); fprintf(f, "%s" " else\n", indent.c_str()); @@ -434,7 +434,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -446,27 +446,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str()); dump_attributes(f, indent, cell->attributes); fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\C"]); + dump_sigspec(f, cell->get("\\C")); fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\R"]); + dump_sigspec(f, cell->get("\\R")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!"); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ")\n"); fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str()); @@ -477,7 +477,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -535,7 +535,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe") { int width = cell->parameters["\\WIDTH"].as_int(); - int s_width = cell->connections_["\\S"].size(); + int s_width = cell->get("\\S").size(); std::string func_name = cellname(cell); fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str()); @@ -567,13 +567,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) fprintf(f, "%s" "endfunction\n", indent.c_str()); fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = %s(", func_name.c_str()); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, ", "); - dump_sigspec(f, cell->connections_["\\S"]); + dump_sigspec(f, cell->get("\\S")); fprintf(f, ");\n"); return true; } @@ -581,9 +581,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$slice") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); return true; } @@ -591,14 +591,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$bu0") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); if (cell->parameters["\\A_SIGNED"].as_bool()) { fprintf(f, " = $signed("); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, ");\n"); } else { fprintf(f, " = { 1'b0, "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); } return true; @@ -607,11 +607,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (cell->type == "$concat") { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Y"]); + dump_sigspec(f, cell->get("\\Y")); fprintf(f, " = { "); - dump_sigspec(f, cell->connections_["\\B"]); + dump_sigspec(f, cell->get("\\B")); fprintf(f, " , "); - dump_sigspec(f, cell->connections_["\\A"]); + dump_sigspec(f, cell->get("\\A")); fprintf(f, " };\n"); return true; } @@ -621,17 +621,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk, sig_arst, val_arst; bool pol_clk, pol_arst = false; - sig_clk = cell->connections_["\\CLK"]; + sig_clk = cell->get("\\CLK"); pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); if (cell->type == "$adff") { - sig_arst = cell->connections_["\\ARST"]; + sig_arst = cell->get("\\ARST"); pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); } std::string reg_name = cellname(cell); - bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name); + bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name); if (!out_is_reg_wire) fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); @@ -660,7 +660,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { fprintf(f, "%s" "assign ", indent.c_str()); - dump_sigspec(f, cell->connections_["\\Q"]); + dump_sigspec(f, cell->get("\\Q")); fprintf(f, " = %s;\n", reg_name.c_str()); } @@ -707,7 +707,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (it->first != str) continue; if (!first_arg) @@ -721,7 +721,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell) break; found_numbered_port:; } - for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) { + for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) { if (numbered_ports.count(it->first)) continue; if (!first_arg) @@ -908,10 +908,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto &it : module->cells) { RTLIL::Cell *cell = it.second; - if (!reg_ct.cell_known(cell->type) || cell->connections_.count("\\Q") == 0) + if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0) continue; - RTLIL::SigSpec sig = cell->connections_["\\Q"]; + RTLIL::SigSpec sig = cell->get("\\Q"); if (sig.is_chunk()) { RTLIL::SigChunk chunk = sig.as_chunk(); @@ -961,7 +961,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second); - for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) + for (auto it = module->connections().begin(); it != module->connections().end(); it++) dump_conn(f, indent + " ", it->first, it->second); fprintf(f, "%s" "endmodule\n", indent.c_str()); |