diff options
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e1962119c..413566699 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -76,6 +76,7 @@ void aiger_encode(std::ostream &f, int x) struct XAigerWriter { + Design *design; Module *module; SigMap sigmap; @@ -138,7 +139,7 @@ struct XAigerWriter return a; } - XAigerWriter(Module *module, bool dff_mode) : module(module), sigmap(module) + XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module) { pool<SigBit> undriven_bits; pool<SigBit> unused_bits; @@ -240,15 +241,16 @@ struct XAigerWriter continue; } - RTLIL::Module* inst_module = module->design->module(cell->type); - if (inst_module) { + RTLIL::Module* inst_module = design->module(cell->type); + if (inst_module && inst_module->get_blackbox_attribute()) { IdString derived_type; if (cell->parameters.empty()) derived_type = cell->type; else - derived_type = inst_module->derive(module->design, cell->parameters); - inst_module = module->design->module(derived_type); + derived_type = inst_module->derive(design, cell->parameters); + inst_module = design->module(derived_type); log_assert(inst_module); + log_assert(inst_module->get_blackbox_attribute()); bool abc9_flop = false; if (!cell->has_keep_attr()) { @@ -326,9 +328,9 @@ struct XAigerWriter for (auto cell : box_list) { log_assert(cell); - RTLIL::Module* box_module = module->design->module(cell->type); + RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - log_assert(box_module->attributes.count(ID::abc9_box_id)); + log_assert(box_module->has_attribute(ID::abc9_box_id)); auto r = box_ports.insert(cell->type); if (r.second) { @@ -576,23 +578,23 @@ struct XAigerWriter for (auto cell : box_list) { log_assert(cell); - RTLIL::Module* box_module = module->design->module(cell->type); + RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); IdString derived_type; if (cell->parameters.empty()) derived_type = cell->type; else - derived_type = box_module->derive(module->design, cell->parameters); - box_module = box_module->design->module(derived_type); - log_assert(box_module); + derived_type = box_module->derive(design, cell->parameters); + auto derived_module = design->module(derived_type); + log_assert(derived_module); auto r = cell_cache.insert(derived_type); auto &v = r.first->second; if (r.second) { int box_inputs = 0, box_outputs = 0; - for (auto port_name : box_module->ports) { - RTLIL::Wire *w = box_module->wire(port_name); + for (auto port_name : derived_module->ports) { + RTLIL::Wire *w = derived_module->wire(port_name); log_assert(w); if (w->port_input) box_inputs += GetSize(w); @@ -602,7 +604,7 @@ struct XAigerWriter std::get<0>(v) = box_inputs; std::get<1>(v) = box_outputs; - std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int(); + std::get<2>(v) = derived_module->attributes.at(ID::abc9_box_id).as_int(); } write_h_buffer(std::get<0>(v)); @@ -699,10 +701,10 @@ struct XAigerWriter f << stringf("Generated by %s\n", yosys_version_str); - module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size()); - module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size()); - module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size()); - module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size()); + design->scratchpad_set_int("write_xaiger.num_ands", and_map.size()); + design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size()); + design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size()); + design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size()); } void write_map(std::ostream &f) |