diff options
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 20 |
1 files changed, 7 insertions, 13 deletions
@@ -364,25 +364,19 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. -- The module attribute ``abc9_box_id`` specifies a positive integer linking a - blackbox or whitebox definition to a corresponding entry in a `abc9` - box-file. +- The module attribute ``abc9_lut`` is an integer attribute indicating to + `abc9` that this module describes a LUT with an area cost of this value, and + propagation delays described using `specify` statements. + +- The module attribute ``abc9_box`` is a boolean specifying a black/white-box + definition, with propagation delays described using `specify` statements, for + use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. -- The output port attribute ``abc9_arrival`` specifies an integer, or a string - of space-separated integers to be used as the arrival time of this blackbox - port. It can be used, for example, to specify the clk-to-Q delay of a flip- - flop output for consideration during `abc9` techmapping. - -- The input port attribute ``abc9_required`` specifies an integer, or a string - of space-separated integers to be used as the required time of this blackbox - port. It can be used, for example, to specify the setup-time of a flip-flop - input for consideration during `abc9` techmapping. - - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform sequential synthesis. |