diff options
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 31 |
1 files changed, 24 insertions, 7 deletions
@@ -3,6 +3,17 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -16,12 +27,18 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "shregmap -tech xilinx" - Added "read_aiger" frontend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - - Added "synth_xilinx -abc9" (experimental) - - Added "synth_ice40 -abc9" (experimental) - - Added "synth -abc9" (experimental) - - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - Added "muxcover -mux{4,8,16}=<cost>" + - Added "muxcover -dmux=<cost>" + - Added "muxcover -nopartial" + - Added "muxpack" pass + - Added "pmux2shiftx -norange" + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - Added "synth_ecp5 -nowidelut" + - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) + - Fixed sign extension of unsized constants with 'bx and 'bz MSB Yosys 0.7 .. Yosys 0.8 @@ -35,7 +52,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts @@ -44,7 +61,7 @@ Yosys 0.7 .. Yosys 0.8 - Added Verilog $rtoi and $itor support - Added "check -initdrv" - Added "read_blif -wideports" - - Added support for systemVerilog "++" and "--" operators + - Added support for SystemVerilog "++" and "--" operators - Added support for SystemVerilog unique, unique0, and priority case - Added "write_edif" options for edif "flavors" - Added support for resetall compiler directive |