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-rw-r--r--Makefile2
-rw-r--r--frontends/verific/verific.cc1
-rw-r--r--passes/cmds/stat.cc156
-rw-r--r--techlibs/achronix/speedster22i/cells_sim.v3
-rw-r--r--techlibs/sf2/cells_sim.v2
-rw-r--r--tests/simple/memory.v14
6 files changed, 107 insertions, 71 deletions
diff --git a/Makefile b/Makefile
index 72da2e5ac..2a82ebbad 100644
--- a/Makefile
+++ b/Makefile
@@ -131,7 +131,7 @@ LDLIBS += -lrt
endif
endif
-YOSYS_VER := 0.21+10
+YOSYS_VER := 0.21+18
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5eb4857c5..6e95fde7b 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1176,6 +1176,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
memory->name = RTLIL::escape_id(net->Name());
log_assert(module->count_id(memory->name) == 0);
module->memories[memory->name] = memory;
+ import_attributes(memory->attributes, net, nl);
int number_of_bits = net->Size();
int bits_in_word = number_of_bits;
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index a4984597d..a998ab8e7 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -149,6 +149,78 @@ struct statdata_t
}
}
+ unsigned int estimate_xilinx_lc()
+ {
+ unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
+ unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
+ unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
+ unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
+ unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
+ unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
+ unsigned int lc_cnt = 0;
+
+ lc_cnt += lut6_cnt;
+
+ lc_cnt += lut5_cnt;
+ if (lut1_cnt) {
+ int cnt = std::min(lut5_cnt, lut1_cnt);
+ lut5_cnt -= cnt;
+ lut1_cnt -= cnt;
+ }
+
+ lc_cnt += lut4_cnt;
+ if (lut1_cnt) {
+ int cnt = std::min(lut4_cnt, lut1_cnt);
+ lut4_cnt -= cnt;
+ lut1_cnt -= cnt;
+ }
+ if (lut2_cnt) {
+ int cnt = std::min(lut4_cnt, lut2_cnt);
+ lut4_cnt -= cnt;
+ lut2_cnt -= cnt;
+ }
+
+ lc_cnt += lut3_cnt;
+ if (lut1_cnt) {
+ int cnt = std::min(lut3_cnt, lut1_cnt);
+ lut3_cnt -= cnt;
+ lut1_cnt -= cnt;
+ }
+ if (lut2_cnt) {
+ int cnt = std::min(lut3_cnt, lut2_cnt);
+ lut3_cnt -= cnt;
+ lut2_cnt -= cnt;
+ }
+ if (lut3_cnt) {
+ int cnt = (lut3_cnt + 1) / 2;
+ lut3_cnt -= cnt;
+ }
+
+ lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
+
+ return lc_cnt;
+ }
+
+ unsigned int cmos_transistor_count(bool *tran_cnt_exact)
+ {
+ unsigned int tran_cnt = 0;
+ auto &gate_costs = CellCosts::cmos_gate_cost();
+
+ for (auto it : num_cells_by_type) {
+ auto ctype = it.first;
+ auto cnum = it.second;
+
+ if (gate_costs.count(ctype))
+ tran_cnt += cnum * gate_costs.at(ctype);
+ else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
+ tran_cnt += cnum * 16;
+ else
+ *tran_cnt_exact = false;
+ }
+
+ return tran_cnt;
+ }
+
void log_data(RTLIL::IdString mod_name, bool top_mod)
{
log(" Number of wires: %6u\n", num_wires);
@@ -176,74 +248,14 @@ struct statdata_t
if (tech == "xilinx")
{
- unsigned int lut6_cnt = num_cells_by_type[ID(LUT6)];
- unsigned int lut5_cnt = num_cells_by_type[ID(LUT5)];
- unsigned int lut4_cnt = num_cells_by_type[ID(LUT4)];
- unsigned int lut3_cnt = num_cells_by_type[ID(LUT3)];
- unsigned int lut2_cnt = num_cells_by_type[ID(LUT2)];
- unsigned int lut1_cnt = num_cells_by_type[ID(LUT1)];
- unsigned int lc_cnt = 0;
-
- lc_cnt += lut6_cnt;
-
- lc_cnt += lut5_cnt;
- if (lut1_cnt) {
- int cnt = std::min(lut5_cnt, lut1_cnt);
- lut5_cnt -= cnt;
- lut1_cnt -= cnt;
- }
-
- lc_cnt += lut4_cnt;
- if (lut1_cnt) {
- int cnt = std::min(lut4_cnt, lut1_cnt);
- lut4_cnt -= cnt;
- lut1_cnt -= cnt;
- }
- if (lut2_cnt) {
- int cnt = std::min(lut4_cnt, lut2_cnt);
- lut4_cnt -= cnt;
- lut2_cnt -= cnt;
- }
-
- lc_cnt += lut3_cnt;
- if (lut1_cnt) {
- int cnt = std::min(lut3_cnt, lut1_cnt);
- lut3_cnt -= cnt;
- lut1_cnt -= cnt;
- }
- if (lut2_cnt) {
- int cnt = std::min(lut3_cnt, lut2_cnt);
- lut3_cnt -= cnt;
- lut2_cnt -= cnt;
- }
- if (lut3_cnt) {
- int cnt = (lut3_cnt + 1) / 2;
- lut3_cnt -= cnt;
- }
-
- lc_cnt += (lut2_cnt + lut1_cnt + 1) / 2;
-
log("\n");
- log(" Estimated number of LCs: %10u\n", lc_cnt);
+ log(" Estimated number of LCs: %10u\n", estimate_xilinx_lc());
}
if (tech == "cmos")
{
- unsigned int tran_cnt = 0;
bool tran_cnt_exact = true;
- auto &gate_costs = CellCosts::cmos_gate_cost();
-
- for (auto it : num_cells_by_type) {
- auto ctype = it.first;
- auto cnum = it.second;
-
- if (gate_costs.count(ctype))
- tran_cnt += cnum * gate_costs.at(ctype);
- else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
- tran_cnt += cnum * 16;
- else
- tran_cnt_exact = false;
- }
+ unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
log("\n");
log(" Estimated number of transistors: %10u%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
@@ -273,7 +285,20 @@ struct statdata_t
first_line = false;
}
log("\n");
- log(" }\n");
+ log(" }");
+ if (tech == "xilinx")
+ {
+ log(",\n");
+ log(" \"estimated_num_lc\": %u", estimate_xilinx_lc());
+ }
+ if (tech == "cmos")
+ {
+ bool tran_cnt_exact = true;
+ unsigned int tran_cnt = cmos_transistor_count(&tran_cnt_exact);
+ log(",\n");
+ log(" \"estimated_num_transistors\": \"%u%s\"", tran_cnt, tran_cnt_exact ? "" : "+");
+ }
+ log("\n");
log(" }");
}
};
@@ -352,8 +377,6 @@ struct StatPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
- log_header(design, "Printing statistics.\n");
-
bool width_mode = false, json_mode = false;
RTLIL::Module *top_mod = nullptr;
std::map<RTLIL::IdString, statdata_t> mod_stat;
@@ -391,6 +414,9 @@ struct StatPass : public Pass {
}
extra_args(args, argidx, design);
+ if(!json_mode)
+ log_header(design, "Printing statistics.\n");
+
if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode)
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index 6c87adb94..fc15e0966 100644
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -68,9 +68,8 @@ end
assign dout = combout_rt & 1'b1;
endmodule
-module DFF (output q,
+module DFF (output reg q,
input d, ck);
- reg q;
always @(posedge ck)
q <= d;
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 02335404b..b5438e44c 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -162,7 +162,7 @@ module ARI1 (
wire F1 = INIT[8 + Fsel];
wire Yout = A ? F1 : F0;
assign Y = Yout;
- wire S = FCI ^ Yout;
+ assign S = FCI ^ Yout;
wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
assign FCO = P ? FCI : G;
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index f38bdafd3..b478d9409 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -137,8 +137,13 @@ endmodule
// ----------------------------------------------------------
-module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_sync(clk, rst, idx, din, dout);
+ input clk;
+ input rst;
(* gentb_constant=0 *) wire rst;
+ input [2:0] idx;
+ input [7:0] din;
+ output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
@@ -156,8 +161,13 @@ module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, ou
assign dout = test[idx];
endmodule
-module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_async(clk, rst, idx, din, dout);
+ input clk;
+ input rst;
(* gentb_constant=0 *) wire rst;
+ input [2:0] idx;
+ input [7:0] din;
+ output [7:0] dout;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 03:41:26 +0000