diff options
-rw-r--r-- | backends/aiger/aiger.cc | 112 | ||||
-rw-r--r-- | frontends/ast/ast.cc | 2 | ||||
-rw-r--r-- | frontends/ast/ast.h | 2 | ||||
-rw-r--r-- | frontends/ast/genrtlil.cc | 7 | ||||
-rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
-rw-r--r-- | frontends/verilog/verilog_lexer.l | 3 | ||||
-rw-r--r-- | frontends/verilog/verilog_parser.y | 26 | ||||
-rw-r--r-- | kernel/celltypes.h | 2 | ||||
-rw-r--r-- | kernel/rtlil.cc | 18 | ||||
-rw-r--r-- | kernel/rtlil.h | 2 | ||||
-rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 | ||||
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 | ||||
-rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
-rw-r--r-- | passes/tests/test_cell.cc | 2 | ||||
-rw-r--r-- | techlibs/common/simlib.v | 16 |
15 files changed, 184 insertions, 18 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index ab1fba6f1..02871a6fd 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -46,11 +46,13 @@ struct AigerWriter dict<SigBit, SigBit> not_map, ff_map; dict<SigBit, pair<SigBit, SigBit>> and_map; vector<pair<SigBit, SigBit>> asserts, assumes; + vector<pair<SigBit, SigBit>> liveness, fairness; pool<SigBit> initstate_bits; vector<pair<int, int>> aig_gates; vector<int> aig_latchin, aig_latchinit, aig_outputs; - int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0, aig_b = 0, aig_c = 0; + int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0; + int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0; dict<SigBit, int> aig_map; dict<SigBit, int> ordered_outputs; @@ -163,6 +165,22 @@ struct AigerWriter continue; } + if (cell->type == "$live") + { + SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + liveness.push_back(make_pair(A, EN)); + continue; + } + + if (cell->type == "$fair") + { + SigBit A = sigmap(cell->getPort("\\A").as_bit()); + SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); + fairness.push_back(make_pair(A, EN)); + continue; + } + if (cell->type == "$anyconst") { for (auto bit : sigmap(cell->getPort("\\Y"))) @@ -198,6 +216,12 @@ struct AigerWriter } } + int fair_live_inputs_cnt = GetSize(liveness); + int fair_live_inputs_m = aig_m; + + aig_m += fair_live_inputs_cnt; + aig_i += fair_live_inputs_cnt; + for (auto it : ff_map) { aig_m++, aig_l++; aig_map[it.first] = 2*aig_m; @@ -214,6 +238,16 @@ struct AigerWriter aig_latchinit.push_back(0); } + int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness); + int fair_live_latches_m = aig_m; + int fair_live_latches_l = aig_l; + + aig_m += fair_live_latches_cnt; + aig_l += fair_live_latches_cnt; + + for (int i = 0; i < fair_live_latches_cnt; i++) + aig_latchinit.push_back(0); + if (zinit_mode) { for (auto it : ff_map) @@ -263,23 +297,67 @@ struct AigerWriter int bit_en = bit2aig(it.second); aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1); } + + for (auto it : liveness) + { + int input_m = ++fair_live_inputs_m; + int latch_m1 = ++fair_live_latches_m; + int latch_m2 = ++fair_live_latches_m; + + log_assert(GetSize(aig_latchin) == fair_live_latches_l); + fair_live_latches_l += 2; + + int bit_a = bit2aig(it.first); + int bit_en = bit2aig(it.second); + int bit_s = 2*input_m; + int bit_q1 = 2*latch_m1; + int bit_q2 = 2*latch_m2; + + int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1; + int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1; + + aig_j++; + aig_latchin.push_back(bit_d1); + aig_latchin.push_back(bit_d2); + aig_outputs.push_back(mkgate(bit_q1, bit_q2^1)); + } + + for (auto it : fairness) + { + int latch_m = ++fair_live_latches_m; + + log_assert(GetSize(aig_latchin) == fair_live_latches_l); + fair_live_latches_l += 1; + + int bit_a = bit2aig(it.first); + int bit_en = bit2aig(it.second); + int bit_q = 2*latch_m; + + aig_f++; + aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1)); + aig_outputs.push_back(bit_q^1); + } } void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode) { + int aig_obc = aig_o + aig_b + aig_c; + int aig_obcj = aig_obc + aig_j; + int aig_obcjf = aig_obcj + aig_f; + log_assert(aig_m == aig_i + aig_l + aig_a); log_assert(aig_l == GetSize(aig_latchin)); log_assert(aig_l == GetSize(aig_latchinit)); - log_assert((aig_o + aig_b + aig_c) == GetSize(aig_outputs)); + log_assert(aig_obcjf == GetSize(aig_outputs)); if (miter_mode) { - if (aig_b || aig_c) - log_error("Running AIGER back-end in -miter mode, but design contains $assert and/or $assume cells!\n"); + if (aig_b || aig_c || aig_j || aig_f) + log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n"); f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o); } else { f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a); - if (aig_b || aig_c) - f << stringf(" %d %d", aig_b, aig_c); + if (aig_b || aig_c || aig_j || aig_f) + f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f); f << stringf("\n"); } @@ -297,7 +375,16 @@ struct AigerWriter f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2); } - for (int i = 0; i < aig_o + aig_b + aig_c; i++) + for (int i = 0; i < aig_obc; i++) + f << stringf("%d\n", aig_outputs.at(i)); + + for (int i = aig_obc; i < aig_obcj; i++) + f << stringf("1\n"); + + for (int i = aig_obc; i < aig_obcj; i++) + f << stringf("%d\n", aig_outputs.at(i)); + + for (int i = aig_obcj; i < aig_obcjf; i++) f << stringf("%d\n", aig_outputs.at(i)); for (int i = 0; i < aig_a; i++) @@ -314,7 +401,16 @@ struct AigerWriter f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2); } - for (int i = 0; i < aig_o + aig_b + aig_c; i++) + for (int i = 0; i < aig_obc; i++) + f << stringf("%d\n", aig_outputs.at(i)); + + for (int i = aig_obc; i < aig_obcj; i++) + f << stringf("1\n"); + + for (int i = aig_obc; i < aig_obcj; i++) + f << stringf("%d\n", aig_outputs.at(i)); + + for (int i = aig_obcj; i < aig_obcjf; i++) f << stringf("%d\n", aig_outputs.at(i)); for (int i = 0; i < aig_a; i++) { diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 06660102b..482acd364 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -84,6 +84,8 @@ std::string AST::type2str(AstNodeType type) X(AST_PREFIX) X(AST_ASSERT) X(AST_ASSUME) + X(AST_LIVE) + X(AST_FAIR) X(AST_COVER) X(AST_FCALL) X(AST_TO_BITS) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 0b9116d39..bddda9667 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -65,6 +65,8 @@ namespace AST AST_PREFIX, AST_ASSERT, AST_ASSUME, + AST_LIVE, + AST_FAIR, AST_COVER, AST_FCALL, diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index bdac4de00..78e83e038 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1336,10 +1336,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate $assert cells case AST_ASSERT: case AST_ASSUME: + case AST_LIVE: + case AST_FAIR: case AST_COVER: { - const char *celltype = "$assert"; + const char *celltype = nullptr; + if (type == AST_ASSERT) celltype = "$assert"; if (type == AST_ASSUME) celltype = "$assume"; + if (type == AST_LIVE) celltype = "$live"; + if (type == AST_FAIR) celltype = "$fair"; if (type == AST_COVER) celltype = "$cover"; log_assert(children.size() == 2); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index f7fcbc479..28c9945ab 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1400,7 +1400,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } skip_dynamic_range_lvalue_expansion:; - if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && current_block != NULL) + if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL) { std::stringstream sstr; sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++); @@ -1462,7 +1462,7 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && children.size() == 1) + if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1) { children.push_back(mkconst_int(1, false, 1)); did_something = true; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 091c1a029..885332b76 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -191,6 +191,9 @@ YOSYS_NAMESPACE_END "logic" { SV_KEYWORD(TOK_REG); } "bit" { SV_KEYWORD(TOK_REG); } +"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } +"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } + "input" { return TOK_INPUT; } "output" { return TOK_OUTPUT; } "inout" { return TOK_INOUT; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 9b2498694..60b1ecffd 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -116,7 +116,7 @@ static void free_attr(std::map<std::string, AstNode*> *al) %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME %token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF -%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER +%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int @@ -1030,6 +1030,12 @@ assert: TOK_ASSUME '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3)); } | + TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4)); + } | + TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4)); + } | TOK_COVER '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3)); } | @@ -1044,6 +1050,12 @@ assert: delete $3; else ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3)); + } | + TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' { + if (norestrict_mode) + delete $4; + else + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4)); }; assert_property: @@ -1053,6 +1065,12 @@ assert_property: TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); } | + TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5)); + } | + TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); + } | TOK_COVER TOK_PROPERTY '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4)); } | @@ -1061,6 +1079,12 @@ assert_property: delete $4; else ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); + } | + TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' { + if (norestrict_mode) + delete $5; + else + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); }; simple_behavioral_stmt: diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 8f31d0172..c43f685ac 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -116,6 +116,8 @@ struct CellTypes setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true); setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true); + setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true); + setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true); setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true); setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true); setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 978a7a537..6ce3f1376 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1026,7 +1026,7 @@ namespace { return; } - if (cell->type.in("$assert", "$assume", "$cover")) { + if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) { port("\\A", 1); port("\\EN", 1); check_expected(); @@ -1819,6 +1819,22 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a return cell; } +RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) +{ + RTLIL::Cell *cell = addCell(name, "$live"); + cell->setPort("\\A", sig_a); + cell->setPort("\\EN", sig_en); + return cell; +} + +RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) +{ + RTLIL::Cell *cell = addCell(name, "$fair"); + cell->setPort("\\A", sig_a); + cell->setPort("\\EN", sig_en); + return cell; +} + RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en) { RTLIL::Cell *cell = addCell(name, "$cover"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 7a6f5717d..ab8771256 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1007,6 +1007,8 @@ public: RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y); RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); + RTLIL::Cell* addLive (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); + RTLIL::Cell* addFair (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); RTLIL::Cell* addCover (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en); RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y); diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 7686f5963..b2ba1fd88 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. \end{fixme} \begin{fixme} diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3534cbcdb..d71e9c574 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover")) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover")) return cache[mod] = true; } return cache[mod]; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 65944caec..c426c4bf2 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -64,7 +64,7 @@ struct keep_cache_t bool query(Cell *cell) { - if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$cover")) + if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover")) return true; if (cell->has_keep_attr()) diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 049c20533..47b6bdf23 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -852,8 +852,6 @@ struct TestCellPass : public Pass { // cell_types["$slice"] = "A"; // cell_types["$concat"] = "A"; - // cell_types["$assert"] = "A"; - // cell_types["$assume"] = "A"; cell_types["$lut"] = "*"; cell_types["$sop"] = "*"; diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index d0abd3b34..276503fe8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,6 +1305,22 @@ endmodule // -------------------------------------------------------- +module \$live (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + +module \$fair (A, EN); + +input A, EN; + +endmodule + +// -------------------------------------------------------- + module \$cover (A, EN); input A, EN; |