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-rw-r--r--backends/blif/blif.cc2
-rw-r--r--backends/verilog/verilog_backend.cc2
-rw-r--r--frontends/liberty/liberty.cc22
-rw-r--r--frontends/verific/verific.cc6
-rw-r--r--kernel/celltypes.h4
-rw-r--r--kernel/rtlil.cc4
-rw-r--r--kernel/rtlil.h4
-rw-r--r--kernel/satgen.h2
-rw-r--r--manual/CHAPTER_CellLib.tex4
-rw-r--r--manual/CHAPTER_StateOfTheArt/simlib_yosys.v4
-rw-r--r--manual/PRESENTATION_ExSyn.tex2
-rw-r--r--manual/PRESENTATION_Prog.tex2
-rw-r--r--passes/abc/abc.cc4
-rw-r--r--passes/opt/opt_const.cc12
-rw-r--r--passes/sat/freduce.cc4
-rw-r--r--passes/techmap/dfflibmap.cc2
-rw-r--r--passes/techmap/simplemap.cc8
-rw-r--r--techlibs/common/simcells.v4
-rw-r--r--techlibs/common/techmap.v2
19 files changed, 47 insertions, 47 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 5daab6691..386d68d8b 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -143,7 +143,7 @@ struct BlifDumper
{
RTLIL::Cell *cell = cell_it.second;
- if (!config->icells_mode && cell->type == "$_INV_") {
+ if (!config->icells_mode && cell->type == "$_NOT_") {
fprintf(f, ".names %s %s\n0 1\n",
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
continue;
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index cafc1f3f0..81c938bdd 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -370,7 +370,7 @@ void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s
bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
{
- if (cell->type == "$_INV_") {
+ if (cell->type == "$_NOT_") {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 504b8d1e4..83bfce371 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -55,7 +55,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", A);
cell->setPort("\\Y", module->addWire(NEW_ID));
return cell->getPort("\\Y");
@@ -241,17 +241,17 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clk_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clk_sig) {
clk_sig = it.second->getPort("\\A");
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clear_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
clear_sig = it.second->getPort("\\A");
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == preset_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
preset_sig = it.second->getPort("\\A");
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
@@ -259,7 +259,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", iq_sig);
cell->setPort("\\Y", iqn_sig);
@@ -318,17 +318,17 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == enable_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == enable_sig) {
enable_sig = it.second->getPort("\\A");
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clear_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == clear_sig) {
clear_sig = it.second->getPort("\\A");
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == preset_sig) {
+ if (it.second->type == "$_NOT_" && it.second->getPort("\\Y") == preset_sig) {
preset_sig = it.second->getPort("\\A");
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
@@ -336,7 +336,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
cell->setPort("\\A", iq_sig);
cell->setPort("\\Y", iqn_sig);
@@ -347,7 +347,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
if (clear_polarity == true || clear_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
inv->setPort("\\A", clear_sig);
inv->setPort("\\Y", module->addWire(NEW_ID));
@@ -375,7 +375,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
if (preset_polarity == false || preset_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
inv->setPort("\\A", preset_sig);
inv->setPort("\\Y", module->addWire(NEW_ID));
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1ffcc4229..95b3c407e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -162,7 +162,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == PRIM_NAND) {
RTLIL::SigSpec tmp = module->addWire(NEW_ID);
module->addAndGate(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), tmp);
- module->addInvGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput()));
+ module->addNotGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput()));
return true;
}
@@ -174,7 +174,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
if (inst->Type() == PRIM_NOR) {
RTLIL::SigSpec tmp = module->addWire(NEW_ID);
module->addOrGate(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), tmp);
- module->addInvGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput()));
+ module->addNotGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput()));
return true;
}
@@ -184,7 +184,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*,
}
if (inst->Type() == PRIM_INV) {
- module->addInvGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
+ module->addNotGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
return true;
}
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 5486f6acb..e30ceb8b1 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -130,7 +130,7 @@ struct CellTypes
void setup_stdcells()
{
- setup_type("$_INV_", {"\\A"}, {"\\Y"}, false);
+ setup_type("$_NOT_", {"\\A"}, {"\\Y"}, false);
setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, false);
setup_type("$_OR_", {"\\A", "\\B"}, {"\\Y"}, false);
setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, false);
@@ -241,7 +241,7 @@ struct CellTypes
HANDLE_CELL_TYPE(neg)
#undef HANDLE_CELL_TYPE
- if (type == "$_INV_")
+ if (type == "$_NOT_")
return const_not(arg1, arg2, false, false, 1);
if (type == "$_AND_")
return const_and(arg1, arg2, false, false, 1);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f4f32f600..614ea770b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -758,7 +758,7 @@ namespace {
return;
}
- if (cell->type == "$_INV_") { check_gate("AY"); return; }
+ if (cell->type == "$_NOT_") { check_gate("AY"); return; }
if (cell->type == "$_AND_") { check_gate("ABY"); return; }
if (cell->type == "$_OR_") { check_gate("ABY"); return; }
if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
@@ -1338,7 +1338,7 @@ DEF_METHOD(Pmux, "$pmux", 1)
add ## _func(name, sig1, sig2, sig3, sig4); \
return sig4; \
}
-DEF_METHOD_2(InvGate, "$_INV_", A, Y)
+DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 2c4b26f53..43e36cbde 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -694,7 +694,7 @@ public:
RTLIL::Cell* addDlatchsr (RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true);
- RTLIL::Cell* addInvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y);
+ RTLIL::Cell* addNotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y);
RTLIL::Cell* addAndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
RTLIL::Cell* addOrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
RTLIL::Cell* addXorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
@@ -757,7 +757,7 @@ public:
RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
- RTLIL::SigSpec InvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a);
+ RTLIL::SigSpec NotGate (RTLIL::IdString name, RTLIL::SigSpec sig_a);
RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b);
RTLIL::SigSpec OrGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b);
RTLIL::SigSpec XorGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 8284cdeb2..b57edd9fe 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -271,7 +271,7 @@ struct SatGen
return true;
}
- if (cell->type == "$_INV_" || cell->type == "$not")
+ if (cell->type == "$_NOT_" || cell->type == "$not")
{
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index f05c1b7ad..ea4ae8d40 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -371,7 +371,7 @@ source tree.
\begin{tabular}[t]{ll}
Verilog & Cell Type \\
\hline
-\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_INV\_} \\
+\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_NOT\_} \\
\lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
\lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\
\lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
@@ -398,7 +398,7 @@ $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
\end{table}
Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types
-{\tt \$\_INV\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_}
+{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_}
are used to model combinatorial logic. The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_}
represent d-type flip-flops.
diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
index a2df8f648..54c076614 100644
--- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
@@ -20,12 +20,12 @@
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
- * logic cells (_INV_, _AND_, ...) that are generated by the default technology
+ * logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*
*/
-module _INV_(A, Y);
+module _NOT_(A, Y);
input A;
output Y;
assign Y = ~A;
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f68b6f984..803982295 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -367,7 +367,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis
\bigskip
\begin{block}{The built-in logic gate types are:}
-{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
+{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
\end{block}
\bigskip
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index 3b2145444..4e9f4b21e 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -303,7 +303,7 @@ cell name from the internal cell library:
$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
$reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
-$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_INV_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
+$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
$_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
$_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
$_DFFSR_PNP_ $_DFFSR_PPN_ $_DFFSR_PPP_ $_DLATCH_N_ $_DLATCH_P_ $_DLATCHSR_NNN_ $_DLATCHSR_NNP_
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index e7da6ed4a..2b1d49810 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -130,7 +130,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
return;
}
- if (cell->type == "$_INV_")
+ if (cell->type == "$_NOT_")
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
@@ -733,7 +733,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
continue;
}
if (c->type == "\\INV") {
- RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_NOT_");
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
design->select(module, cell);
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index a13bb09cb..9af1e6bdf 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -209,7 +209,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
- if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") &&
+ if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") &&
cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
if (ct_combinational.cell_known(cell->type))
@@ -371,9 +371,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
}
}
- if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
+ if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
- cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str());
+ cover_list("opt.opt_const.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
goto next_cell;
}
@@ -389,7 +389,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
goto next_cell;
}
- if (cell->type == "$_INV_") {
+ if (cell->type == "$_NOT_") {
RTLIL::SigSpec input = cell->getPort("\\A");
assign_map.apply(input);
if (input.match("1")) ACTION_DO_Y(0);
@@ -463,7 +463,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
if (input.match("10 ")) {
cover("opt.opt_const.mux_to_inv");
- cell->type = "$_INV_";
+ cell->type = "$_NOT_";
cell->setPort("\\A", input.extract(0, 1));
cell->unsetPort("\\B");
cell->unsetPort("\\S");
@@ -648,7 +648,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->parameters.erase("\\WIDTH");
cell->type = "$not";
} else
- cell->type = "$_INV_";
+ cell->type = "$_NOT_";
OPT_DID_SOMETHING = true;
did_something = true;
goto next_cell;
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 7b9fb2072..bfed0005d 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -623,7 +623,7 @@ struct FreduceWorker
batches.push_back(outputs);
bits_full_total += outputs.size();
}
- if (inv_mode && it.second->type == "$_INV_")
+ if (inv_mode && it.second->type == "$_NOT_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
}
@@ -718,7 +718,7 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_ID);
- RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
inv_cell->setPort("\\A", grp[0].bit);
inv_cell->setPort("\\Y", inv_sig);
}
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 16518b7df..6ce771ac4 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -411,7 +411,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
- sig = module->InvGate(NEW_ID, sig);
+ sig = module->NotGate(NEW_ID, sig);
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 960578b06..f5d9bbeef 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -34,7 +34,7 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\Y", sig_y[i]);
}
@@ -74,7 +74,7 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_t[i]);
gate->setPort("\\Y", sig_y[i]);
}
@@ -152,7 +152,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$reduce_xnor") {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_t);
last_output_cell = gate;
@@ -207,7 +207,7 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
- RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_a);
gate->setPort("\\Y", sig_y);
}
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index d492c2f15..7c8a47ddd 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -20,12 +20,12 @@
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
- * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
+ * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/
-module \$_INV_ (A, Y);
+module \$_NOT_ (A, Y);
input A;
output Y;
assign Y = ~A;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 7a4f6b272..190002c01 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -20,7 +20,7 @@
* The internal logic cell technology mapper.
*
* This verilog library contains the mapping of internal cells (e.g. $not with
- * variable bit width) to the internal logic cells (such as the single bit $_INV_
+ * variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.
*
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 22:01:23 +0000