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| -rw-r--r-- | tests/sat/initval.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..337aa9343 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,13 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output o, p); +(* init = 1'bx *) +wire p = o; +$_DFF_P_ dff (.C(clk), .D(i), .Q(o)); +endmodule +EOT +sat -seq 1 |