diff options
| -rw-r--r-- | frontends/verilog/preproc.cc | 2 | ||||
| -rw-r--r-- | kernel/satgen.h | 2 | ||||
| -rw-r--r-- | kernel/yosys.h | 2 | ||||
| -rw-r--r-- | passes/cmds/show.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 6 |
5 files changed, 8 insertions, 6 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index f83433219..7e14fcb84 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -422,7 +422,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (tok == "(" || tok == "{" || tok == "[") level++; } - for (size_t i = 0; i < args.size(); i++) + for (int i = 0; i < GetSize(args); i++) defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i]; } else { insert_input(tok); diff --git a/kernel/satgen.h b/kernel/satgen.h index 779c97506..d556f4f32 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -68,7 +68,7 @@ struct SatGen else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); } else { - std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset); + std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset)); vec.push_back(ez->frozen_literal(name)); imported_signals[pf][bit] = vec.back(); } diff --git a/kernel/yosys.h b/kernel/yosys.h index c5da9f046..d3f885644 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -82,7 +82,7 @@ namespace RTLIL { struct Cell; } -std::string stringf(const char *fmt, ...); +std::string stringf(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); std::string vstringf(const char *fmt, va_list ap); template<typename T> int GetSize(const T &obj) { return obj.size(); } int GetSize(RTLIL::Wire *wire); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index abe6cd460..1599879a1 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -72,7 +72,7 @@ struct ShowWorker { if (currentColor == 0) return "color=\"black\""; - return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1); + return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1, currentColor%8+1); } std::string nextColor(std::string presetColor) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0ee45ba39..73da6ce1d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -109,8 +109,10 @@ struct TechmapWorker connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); - } else - connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); + } else { + connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i); + constmap_info += stringf("|%s %d", log_id(conn.first), i); + } } return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); |