diff options
| -rw-r--r-- | backends/firrtl/firrtl.cc | 3 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 | ||||
| -rw-r--r-- | tests/simple/xfirrtl | 1 |
3 files changed, 3 insertions, 3 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 88c1038b7..eef6401b2 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -165,8 +165,7 @@ struct FirrtlWorker std::string fid(RTLIL::IdString internal_id) { - const char *str = internal_id.c_str(); - return *str == '\\' ? str + 1 : str; + return make_id(internal_id); } std::string cellname(RTLIL::Cell *cell) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c11d885d..3632f348f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -252,7 +252,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "edif")) { if (!edif_file.empty()) - Pass::call(design, stringf("write_edif %s", edif_file.c_str())); + Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str())); } if (check_label(active, run_from, run_to, "blif")) { diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 5bc75347b..50d693513 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,6 +1,7 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of dff_different_styles.v +dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff |