diff options
-rw-r--r-- | backends/edif/edif.cc | 9 | ||||
-rw-r--r-- | kernel/consteval.h | 7 | ||||
-rw-r--r-- | kernel/rtlil.cc | 41 | ||||
-rw-r--r-- | kernel/rtlil.h | 3 | ||||
-rw-r--r-- | kernel/satgen.h | 10 | ||||
-rw-r--r-- | kernel/sigtools.h | 225 | ||||
-rw-r--r-- | manual/CHAPTER_Prog/stubnets.cc | 19 | ||||
-rw-r--r-- | passes/abc/abc.cc | 53 | ||||
-rw-r--r-- | passes/opt/opt_clean.cc | 17 | ||||
-rw-r--r-- | passes/opt/opt_const.cc | 14 | ||||
-rw-r--r-- | passes/opt/opt_muxtree.cc | 12 | ||||
-rw-r--r-- | passes/opt/opt_reduce.cc | 36 | ||||
-rw-r--r-- | passes/sat/eval.cc | 8 | ||||
-rw-r--r-- | passes/sat/sat.cc | 6 | ||||
-rw-r--r-- | passes/techmap/extract.cc | 57 | ||||
-rw-r--r-- | passes/techmap/simplemap.cc | 143 |
16 files changed, 231 insertions, 429 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 74cf24997..3b9a43370 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -306,14 +306,11 @@ struct EdifBackend : public Backend { fprintf(f, ")\n"); for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); - sig.expand(); - for (int i = 0; i < sig.size(); i++) { - RTLIL::SigSpec sigbit(sig.chunks().at(i)); + for (int i = 0; i < SIZE(sig); i++) if (sig.size() == 1) - net_join_db[sigbit].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); + net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else - net_join_db[sigbit].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); - } + net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); } } for (auto &it : net_join_db) { diff --git a/kernel/consteval.h b/kernel/consteval.h index 5836cdd5b..3a8ef44a0 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -71,11 +71,8 @@ struct ConstEval assign_map.apply(sig); #ifndef NDEBUG RTLIL::SigSpec current_val = values_map(sig); - current_val.expand(); - for (size_t i = 0; i < current_val.chunks().size(); i++) { - const RTLIL::SigChunk &chunk = current_val.chunks()[i]; - assert(chunk.wire != NULL || chunk.data.bits[0] == value.bits[i]); - } + for (int i = 0; i < SIZE(current_val); i++) + assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]); #endif values_map.add(sig, RTLIL::SigSpec(value)); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f907ff642..7dcf32b7e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1548,18 +1548,6 @@ bool RTLIL::SigSpec::packed() const return bits_.empty(); } -void RTLIL::SigSpec::expand() -{ - pack(); - std::vector<RTLIL::SigChunk> new_chunks; - for (size_t i = 0; i < chunks_.size(); i++) { - for (int j = 0; j < chunks_[i].width; j++) - new_chunks.push_back(chunks_[i].extract(j, 1)); - } - chunks_.swap(new_chunks); - check(); -} - void RTLIL::SigSpec::optimize() { pack(); @@ -1791,35 +1779,6 @@ void RTLIL::SigSpec::append_bit(const RTLIL::SigBit &bit) // check(); } -bool RTLIL::SigSpec::combine(RTLIL::SigSpec signal, RTLIL::State freeState, bool do_override) -{ - pack(); - signal.pack(); - - bool no_collisions = true; - - assert(width_ == signal.width_); - expand(); - signal.expand(); - - for (size_t i = 0; i < chunks_.size(); i++) { - bool self_free = chunks_[i].wire == NULL && chunks_[i].data.bits[0] == freeState; - bool other_free = signal.chunks_[i].wire == NULL && signal.chunks_[i].data.bits[0] == freeState; - if (!self_free && !other_free) { - if (do_override) - chunks_[i] = signal.chunks_[i]; - else - chunks_[i] = RTLIL::SigChunk(RTLIL::State::Sx, 1); - no_collisions = false; - } - if (self_free && !other_free) - chunks_[i] = signal.chunks_[i]; - } - - optimize(); - return no_collisions; -} - void RTLIL::SigSpec::extend(int width, bool is_signed) { pack(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e1c5b1a6b..6c0a7b66f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -544,7 +544,6 @@ public: inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } - void expand(); void optimize(); RTLIL::SigSpec optimized() const; @@ -567,8 +566,6 @@ public: void append(const RTLIL::SigSpec &signal); void append_bit(const RTLIL::SigBit &bit); - bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool do_override = false); - void extend(int width, bool is_signed = false); void extend_u0(int width, bool is_signed = false); diff --git a/kernel/satgen.h b/kernel/satgen.h index 9e2277076..ea04cb409 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -52,20 +52,18 @@ struct SatGen { log_assert(!undef_mode || model_undef); sigmap->apply(sig); - sig.expand(); std::vector<int> vec; - vec.reserve(sig.chunks().size()); + vec.reserve(SIZE(sig)); - for (auto &c : sig.chunks()) - if (c.wire == NULL) { - RTLIL::State bit = c.data.bits.at(0); + for (auto &bit : sig) + if (bit.wire == NULL) { if (model_undef && dup_undef && bit == RTLIL::State::Sx) vec.push_back(ez->frozen_literal()); else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->TRUE : ez->FALSE); } else { - std::string name = pf + stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset); + std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset); vec.push_back(ez->frozen_literal(name)); } return vec; diff --git a/kernel/sigtools.h b/kernel/sigtools.h index cd179ebf0..1a84194ee 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -27,7 +27,11 @@ struct SigPool { - typedef std::pair<RTLIL::Wire*,int> bitDef_t; + struct bitDef_t : public std::pair<RTLIL::Wire*, int> { + bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { } + }; + std::set<bitDef_t> bits; void clear() @@ -37,14 +41,9 @@ struct SigPool void add(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits.insert(bit); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits.insert(bit); } void add(const SigPool &other) @@ -55,14 +54,9 @@ struct SigPool void del(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits.erase(bit); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits.erase(bit); } void del(const SigPool &other) @@ -73,15 +67,10 @@ struct SigPool void expand(RTLIL::SigSpec from, RTLIL::SigSpec to) { - from.expand(); - to.expand(); - assert(from.chunks().size() == to.chunks().size()); - for (size_t i = 0; i < from.chunks().size(); i++) { - bitDef_t bit_from(from.chunks()[i].wire, from.chunks()[i].offset); - bitDef_t bit_to(to.chunks()[i].wire, to.chunks()[i].offset); - if (bit_from.first == NULL || bit_to.first == NULL) - continue; - if (bits.count(bit_from) > 0) + assert(SIZE(from) == SIZE(to)); + for (int i = 0; i < SIZE(from); i++) { + bitDef_t bit_from(from[i]), bit_to(to[i]); + if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0) bits.insert(bit_to); } } @@ -89,73 +78,49 @@ struct SigPool RTLIL::SigSpec extract(RTLIL::SigSpec sig) { RTLIL::SigSpec result; - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) > 0) - result.append(c); - } + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) + result.append_bit(bit); return result; } RTLIL::SigSpec remove(RTLIL::SigSpec sig) { RTLIL::SigSpec result; - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) == 0) - result.append(c); - } + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit) == 0) + result.append(bit); return result; } bool check_any(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) != 0) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) return true; - } return false; } bool check_all(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit) == 0) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit) == 0) return false; - } return true; } RTLIL::SigSpec export_one() { - RTLIL::SigSpec sig; - for (auto &bit : bits) { - sig.append(RTLIL::SigSpec(bit.first, bit.second)); - break; - } - return sig; + for (auto &bit : bits) + return RTLIL::SigSpec(bit.first, bit.second); + return RTLIL::SigSpec(); } RTLIL::SigSpec export_all() { - RTLIL::SigSpec sig; + std::set<RTLIL::SigBit> sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec(bit.first, bit.second)); - sig.sort_and_unify(); + sig.insert(RTLIL::SigBit(bit.first, bit.second)); return sig; } @@ -168,7 +133,11 @@ struct SigPool template <typename T, class Compare = std::less<T>> struct SigSet { - typedef std::pair<RTLIL::Wire*,int> bitDef_t; + struct bitDef_t : public std::pair<RTLIL::Wire*, int> { + bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { } + }; + std::map<bitDef_t, std::set<T, Compare>> bits; void clear() @@ -178,75 +147,46 @@ struct SigSet void insert(RTLIL::SigSpec sig, T data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].insert(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].insert(data); } void insert(RTLIL::SigSpec sig, const std::set<T> &data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].insert(data.begin(), data.end()); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].insert(data.begin(), data.end()); } void erase(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].clear(); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].clear(); } void erase(RTLIL::SigSpec sig, T data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].erase(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].erase(data); } void erase(RTLIL::SigSpec sig, const std::set<T> &data) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - bits[bit].erase(data.begin(), data.end()); - } + for (auto &bit : sig) + if (bit.wire != NULL) + bits[bit].erase(data.begin(), data.end()); } void find(RTLIL::SigSpec sig, std::set<T> &result) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - for (auto &data : bits[bit]) - result.insert(data); - } + for (auto &bit : sig) + if (bit.wire != NULL) { + auto &data = bits[bit]; + result.insert(data.begin(), data.end()); + } } std::set<T> find(RTLIL::SigSpec sig) @@ -258,22 +198,19 @@ struct SigSet bool has(RTLIL::SigSpec sig) { - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire == NULL) - continue; - assert(c.width == 1); - bitDef_t bit(c.wire, c.offset); - if (bits.count(bit)) + for (auto &bit : sig) + if (bit.wire != NULL && bits.count(bit)) return true; - } return false; } }; struct SigMap { - typedef std::pair<RTLIL::Wire*,int> bitDef_t; + struct bitDef_t : public std::pair<RTLIL::Wire*, int> { + bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { } + }; struct shared_bit_data_t { RTLIL::SigBit map_to; @@ -337,22 +274,20 @@ struct SigMap } // internal helper function - void register_bit(const RTLIL::SigBit &b) + void register_bit(const RTLIL::SigBit &bit) { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) == 0) { + if (bit.wire && bits.count(bit) == 0) { shared_bit_data_t *bd = new shared_bit_data_t; - bd->map_to = b; + bd->map_to = bit; bd->bits.insert(bit); bits[bit] = bd; } } // internal helper function - void unregister_bit(const RTLIL::SigBit &b) + void unregister_bit(const RTLIL::SigBit &bit) { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) > 0) { + if (bit.wire && bits.count(bit) > 0) { shared_bit_data_t *bd = bits[bit]; bd->bits.erase(bit); if (bd->bits.size() == 0) @@ -366,11 +301,8 @@ struct SigMap { assert(bit1.wire != NULL && bit2.wire != NULL); - bitDef_t b1(bit1.wire, bit1.offset); - bitDef_t b2(bit2.wire, bit2.offset); - - shared_bit_data_t *bd1 = bits[b1]; - shared_bit_data_t *bd2 = bits[b2]; + shared_bit_data_t *bd1 = bits[bit1]; + shared_bit_data_t *bd2 = bits[bit2]; assert(bd1 != NULL && bd2 != NULL); if (bd1 == bd2) @@ -394,20 +326,18 @@ struct SigMap } // internal helper function - void set_bit(const RTLIL::SigBit &b1, const RTLIL::SigBit &b2) + void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2) { - assert(b1.wire != NULL); - bitDef_t bit(b1.wire, b1.offset); - assert(bits.count(bit) > 0); - bits[bit]->map_to = b2; + assert(bit1.wire != NULL); + assert(bits.count(bit1) > 0); + bits[bit1]->map_to = bit2; } // internal helper function - void map_bit(RTLIL::SigBit &b) const + void map_bit(RTLIL::SigBit &bit) const { - bitDef_t bit(b.wire, b.offset); - if (b.wire && bits.count(bit) > 0) - b = bits.at(bit)->map_to; + if (bit.wire && bits.count(bit) > 0) + bit = bits.at(bit)->map_to; } void add(RTLIL::SigSpec from, RTLIL::SigSpec to) @@ -446,6 +376,11 @@ struct SigMap unregister_bit(bit); } + void apply(RTLIL::SigBit &bit) const + { + map_bit(bit); + } + void apply(RTLIL::SigSpec &sig) const { for (auto &bit : sig) diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 1c71f78b8..efb3ca958 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -21,7 +21,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re SigMap sigmap(module); // count how many times a single-bit signal is used - std::map<RTLIL::SigSpec, int> bit_usage_count; + std::map<RTLIL::SigBit, int> bit_usage_count; // count ouput lines for this module (needed only for summary output at the end) int line_count = 0; @@ -36,13 +36,10 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // (use sigmap to get a uniqe signal name) RTLIL::SigSpec sig = sigmap(conn.second); - // split the signal up into single-bit chunks - sig.expand(); - - // add each chunk to bit_usage_count, unless it is a constant - for (auto &c : sig.chunks) - if (c.wire != NULL) - bit_usage_count[c]++; + // add each bit to bit_usage_count, unless it is a constant + for (auto &bit : sig) + if (bit.wire != NULL) + bit_usage_count[bit]++; } // for each wire in the module @@ -62,13 +59,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // get a signal description for this wire and split it into seperate bits RTLIL::SigSpec sig = sigmap(wire); - sig.expand(); // for each bit (unless it is a constant): // check if it is used at least two times and add to stub_bits otherwise - for (size_t i = 0; i < sig.chunks.size(); i++) - if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] + - usage_offset) < 2) + for (size_t i = 0; i < SIZE(sig); i++) + if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2) stub_bits.insert(i); // continue if no stub bits found diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 8cdd39b7a..ba27a3fc6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -55,26 +55,23 @@ struct gate_t char type; int in1, in2, in3; bool is_port; - RTLIL::SigSpec sig; + RTLIL::SigBit bit; }; static int map_autoidx; static SigMap assign_map; static RTLIL::Module *module; static std::vector<gate_t> signal_list; -static std::map<RTLIL::SigSpec, int> signal_map; +static std::map<RTLIL::SigBit, int> signal_map; static bool clk_polarity; static RTLIL::SigSpec clk_sig; -static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) +static int map_signal(RTLIL::SigBit bit, char gate_type = -1, int in1 = -1, int in2 = -1, int in3 = -1) { - assert(sig.size() == 1); - assert(sig.chunks().size() == 1); + assign_map.apply(bit); - assign_map.apply(sig); - - if (signal_map.count(sig) == 0) { + if (signal_map.count(bit) == 0) { gate_t gate; gate.id = signal_list.size(); gate.type = -1; @@ -82,12 +79,12 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int gate.in2 = -1; gate.in3 = -1; gate.is_port = false; - gate.sig = sig; + gate.bit = bit; signal_list.push_back(gate); - signal_map[sig] = gate.id; + signal_map[bit] = gate.id; } - gate_t &gate = signal_list[signal_map[sig]]; + gate_t &gate = signal_list[signal_map[bit]]; if (gate_type >= 0) gate.type = gate_type; @@ -103,12 +100,9 @@ static int map_signal(RTLIL::SigSpec sig, char gate_type = -1, int in1 = -1, int static void mark_port(RTLIL::SigSpec sig) { - assign_map.apply(sig); - sig.expand(); - for (auto &c : sig.chunks()) { - if (c.wire != NULL && signal_map.count(c) > 0) - signal_list[signal_map[c]].is_port = true; - } + for (auto &bit : assign_map(sig)) + if (bit.wire != NULL && signal_map.count(bit) > 0) + signal_list[signal_map[bit]].is_port = true; } static void extract_cell(RTLIL::Cell *cell, bool keepff) @@ -229,7 +223,7 @@ static void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edge } for (auto n : nodes) - fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].sig), + fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) @@ -280,7 +274,7 @@ static void handle_loops() int id = *workpool.begin(); workpool.erase(id); - // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].sig)); + // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit)); for (int id2 : edges[id]) { assert(in_edges_count[id2] > 0); @@ -300,8 +294,8 @@ static void handle_loops() for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].sig.chunks()[0].wire; - RTLIL::Wire *w2 = signal_list[id2].sig.chunks()[0].wire; + RTLIL::Wire *w1 = signal_list[id1].bit.wire; + RTLIL::Wire *w2 = signal_list[id2].bit.wire; if (w1 != NULL) continue; else if (w2 == NULL) @@ -333,10 +327,10 @@ static void handle_loops() for (int id2 : edges[id1]) { if (first_line) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), - log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig)); + log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); else log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", - log_signal(signal_list[id1].sig), log_signal(signal_list[id2].sig)); + log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); first_line = false; } @@ -357,7 +351,7 @@ static void handle_loops() } edges[id1].swap(edges[id3]); - module->connections.push_back(RTLIL::SigSig(signal_list[id3].sig, signal_list[id1].sig)); + module->connections.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } @@ -549,13 +543,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std fprintf(f, "\n"); for (auto &si : signal_list) - fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.sig)); + fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit)); for (auto &si : signal_list) { - assert(si.sig.size() == 1 && si.sig.chunks().size() == 1); - if (si.sig.chunks()[0].wire == NULL) { + if (si.bit.wire == NULL) { fprintf(f, ".names n%d\n", si.id); - if (si.sig.chunks()[0].data.bits[0] == RTLIL::State::S1) + if (si.bit == RTLIL::State::S1) fprintf(f, "1\n"); } } @@ -837,12 +830,12 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std snprintf(buffer, 100, "\\n%d", si.id); RTLIL::SigSig conn; if (si.type >= 0) { - conn.first = si.sig; + conn.first = si.bit; conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]); out_wires++; } else { conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]); - conn.second = si.sig; + conn.second = si.bit; in_wires++; } module->connections.push_back(conn); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 23fc48d5d..0be36606d 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -233,14 +233,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { del_wires.push_back(wire); } else { - s1.expand(); - s2.expand(); - assert(s1.chunks().size() == s2.chunks().size()); + assert(SIZE(s1) == SIZE(s2)); RTLIL::SigSig new_conn; - for (size_t i = 0; i < s1.chunks().size(); i++) - if (s1.chunks()[i] != s2.chunks()[i]) { - new_conn.first.append(s1.chunks()[i]); - new_conn.second.append(s2.chunks()[i]); + for (int i = 0; i < SIZE(s1); i++) + if (s1[i] != s2[i]) { + new_conn.first.append_bit(s1[i]); + new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { new_conn.first.optimize(); @@ -257,9 +255,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; - sig.expand(); - for (size_t i = 0; i < sig.chunks().size(); i++) { - if (sig.chunks()[i].wire == NULL) + for (int i = 0; i < SIZE(sig); i++) { + if (sig[i].wire == NULL) continue; if (!used_signals_nodrivers.check_any(sig)) { if (!unused_bits.empty()) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 9b89291b1..ff139854f 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -458,21 +458,19 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } RTLIL::SigSpec new_a, new_b; - a.expand(), b.expand(); - assert(a.chunks().size() == b.chunks().size()); - for (size_t i = 0; i < a.chunks().size(); i++) { - if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] && - a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) { + assert(SIZE(a) == SIZE(b)); + for (int i = 0; i < SIZE(a); i++) { + if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell; } - if (a.chunks()[i] == b.chunks()[i]) + if (a[i] == b[i]) continue; - new_a.append(a.chunks()[i]); - new_b.append(b.chunks()[i]); + new_a.append(a[i]); + new_b.append(b[i]); } if (new_a.size() == 0) { diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 61147f67a..dfcd55126 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -36,7 +36,11 @@ struct OptMuxtreeWorker SigMap assign_map; int removed_count; - typedef std::pair<RTLIL::Wire*,int> bitDef_t; + struct bitDef_t : public std::pair<RTLIL::Wire*, int> { + bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { } + bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { } + }; + struct bitinfo_t { int num; @@ -259,10 +263,8 @@ struct OptMuxtreeWorker { std::vector<int> results; assign_map.apply(sig); - sig.expand(); - for (auto &c : sig.chunks()) - if (c.wire != NULL) { - bitDef_t bit(c.wire, c.offset); + for (auto &bit : sig) + if (bit.wire != NULL) { if (bit2num.count(bit) == 0) { bitinfo_t info; info.num = bit2info.size(); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 7ab7233c6..913855f48 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -44,46 +44,48 @@ struct OptReduceWorker cells.erase(cell); RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]); - sig_a.sort_and_unify(); - sig_a.expand(); + std::set<RTLIL::SigBit> new_sig_a_bits; - RTLIL::SigSpec new_sig_a; - for (auto &chunk : sig_a.chunks()) + for (auto &bit : sig_a.to_sigbit_set()) { - if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) { + if (bit == RTLIL::State::S0) { if (cell->type == "$reduce_and") { - new_sig_a = RTLIL::SigSpec(RTLIL::State::S0); + new_sig_a_bits.clear(); + new_sig_a_bits.insert(RTLIL::State::S0); break; } continue; } - if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) { + if (bit == RTLIL::State::S1) { if (cell->type == "$reduce_or") { - new_sig_a = RTLIL::SigSpec(RTLIL::State::S1); + new_sig_a_bits.clear(); + new_sig_a_bits.insert(RTLIL::State::S1); break; } continue; } - if (chunk.wire == NULL) { - new_sig_a.append(chunk); + if (bit.wire == NULL) { + new_sig_a_bits.insert(bit); continue; } bool imported_children = false; - for (auto child_cell : drivers.find(chunk)) { + for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->connections["\\Y"].extract(0, 1) == chunk) - new_sig_a.append(child_cell->connections["\\A"]); - else - new_sig_a.append(RTLIL::State::S0); + if (child_cell->connections["\\Y"][0] == bit) { + std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set(); + new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); + } else + new_sig_a_bits.insert(RTLIL::State::S0); imported_children = true; } } if (!imported_children) - new_sig_a.append(chunk); + new_sig_a_bits.insert(bit); } - new_sig_a.sort_and_unify(); + + RTLIL::SigSpec new_sig_a(new_sig_a_bits); if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 090f7463a..9b8c35361 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -169,10 +169,9 @@ struct VlogHammerReporter if (!ez.solve(y_vec, y_values)) log_error("Failed to find solution to SAT problem.\n"); - expected_y.expand(); for (int i = 0; i < expected_y.size(); i++) { RTLIL::State solution_bit = y_values.at(i) ? RTLIL::State::S1 : RTLIL::State::S0; - RTLIL::State expected_bit = expected_y.chunks().at(i).data.bits.at(0); + RTLIL::State expected_bit = expected_y[i].data; if (model_undef) { if (y_values.at(expected_y.size()+i)) solution_bit = RTLIL::State::Sx; @@ -187,8 +186,7 @@ struct VlogHammerReporter sat_bits += "x"; else sat_bits += y_values.at(k) ? "1" : "0"; - rtl_bits += expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::Sx ? "x" : - expected_y.chunks().at(k).data.bits.at(0) == RTLIL::State::S1 ? "1" : "0"; + rtl_bits += expected_y[k] == RTLIL::State::Sx ? "x" : expected_y[k] == RTLIL::State::S1 ? "1" : "0"; } log_error("Found error in SAT model: y[%d] = %s, should be %s:\n SAT: %s\n RTL: %s\n %*s^\n", int(i), log_signal(solution_bit), log_signal(expected_bit), @@ -288,11 +286,9 @@ struct VlogHammerReporter if (module_name == "rtl") { rtl_sig = sig; - rtl_sig.expand(); sat_check(module, recorded_set_vars, recorded_set_vals, sig, false); sat_check(module, recorded_set_vars, recorded_set_vals, sig, true); } else if (rtl_sig.size() > 0) { - sig.expand(); if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); for (int i = 0; i < SIZE(sig); i++) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 24968aa2c..34becaee8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -411,10 +411,8 @@ struct SatHelper if (prove_asserts) { RTLIL::SigSpec asserts_a, asserts_en; satgen.getAsserts(asserts_a, asserts_en, timestep); - asserts_a.expand(); - asserts_en.expand(); - for (size_t i = 0; i < asserts_a.chunks().size(); i++) - log("Import proof for assert: %s when %s.\n", log_signal(asserts_a.chunks()[i]), log_signal(asserts_en.chunks()[i])); + for (int i = 0; i < SIZE(asserts_a); i++) + log("Import proof for assert: %s when %s.\n", log_signal(asserts_a[i]), log_signal(asserts_en[i])); prove_bits.push_back(satgen.importAsserts(timestep)); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index e5055c9c4..4c3aec31d 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -130,11 +130,8 @@ namespace RTLIL::SigSpec needleSig = conn.second; RTLIL::SigSpec haystackSig = haystackCell->connections.at(portMapping.at(conn.first)); - needleSig.expand(); - haystackSig.expand(); - for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { - RTLIL::Wire *needleWire = needleSig.chunks().at(i).wire, *haystackWire = haystackSig.chunks().at(i).wire; + RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) return false; @@ -156,7 +153,7 @@ namespace int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL) { SigMap sigmap(mod); - std::map<RTLIL::SigChunk, bit_ref_t> sig_bit_ref; + std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref; if (sel && !sel->selected(mod)) { log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name)); @@ -192,10 +189,9 @@ namespace for (auto &conn : cell->connections) { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (chunk.wire != NULL) - sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++; + for (auto &bit : conn_sig) + if (bit.wire != NULL) + sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++; } } @@ -220,39 +216,37 @@ namespace RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (size_t i = 0; i < conn_sig.chunks().size(); i++) + for (int i = 0; i < conn_sig.size(); i++) { - auto &chunk = conn_sig.chunks()[i]; - assert(chunk.width == 1); + auto &bit = conn_sig[i]; - if (chunk.wire == NULL) { + if (bit.wire == NULL) { if (constports) { std::string node = "$const$x"; - if (chunk.data.bits[0] == RTLIL::State::S0) node = "$const$0"; - if (chunk.data.bits[0] == RTLIL::State::S1) node = "$const$1"; - if (chunk.data.bits[0] == RTLIL::State::Sz) node = "$const$z"; + if (bit == RTLIL::State::S0) node = "$const$0"; + if (bit == RTLIL::State::S1) node = "$const$1"; + if (bit == RTLIL::State::Sz) node = "$const$z"; graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0); } else - graph.createConstant(cell->name, conn.first, i, int(chunk.data.bits[0])); + graph.createConstant(cell->name, conn.first, i, int(bit.data)); continue; } - if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout) + if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout) continue; - if (sel && !sel->selected(mod, chunk.wire)) + if (sel && !sel->selected(mod, bit.wire)) continue; - if (sig_bit_ref.count(chunk) == 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + if (sig_bit_ref.count(bit) == 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; bit_ref.cell = cell->name; bit_ref.port = conn.first; bit_ref.bit = i; } - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i); } } @@ -267,11 +261,10 @@ namespace { RTLIL::SigSpec conn_sig = conn.second; sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (sig_bit_ref.count(chunk) != 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + for (auto &bit : conn_sig) + if (sig_bit_ref.count(bit) != 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); } } @@ -285,11 +278,10 @@ namespace { RTLIL::SigSpec conn_sig(wire); sigmap.apply(conn_sig); - conn_sig.expand(); - for (auto &chunk : conn_sig.chunks()) - if (sig_bit_ref.count(chunk) != 0) { - bit_ref_t &bit_ref = sig_bit_ref[chunk]; + for (auto &bit : conn_sig) + if (sig_bit_ref.count(bit) != 0) { + bit_ref_t &bit_ref = sig_bit_ref[bit]; graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit); } } @@ -333,9 +325,8 @@ namespace for (auto &conn : needle_cell->connections) { RTLIL::SigSpec sig = sigmap(conn.second); if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) { - sig.expand(); for (int i = 0; i < sig.size(); i++) - for (auto &port : sig2port.find(sig.chunks()[i])) { + for (auto &port : sig2port.find(sig[i])) { RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); cell->connections.at(port.first).replace(port.second, bitsig); } diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 1eb5c063b..034677d3b 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -29,75 +29,60 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); - sig_a.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); - for (int i = 0; i < width; i++) { + sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend(width, cell->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool()); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); + sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + module->connections.push_back(RTLIL::SigSig(sig_y, sig_a)); } static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\Y_WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool()); - sig_a.expand(); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - sig_b.extend_u0(width, cell->parameters.at("\\B_SIGNED").as_bool()); - sig_b.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); + + sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool()); + sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool()); if (cell->type == "$xnor") { - RTLIL::SigSpec sig_t = module->addWire(NEW_ID, width); - sig_t.expand(); + RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y)); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_INV_"; - gate->connections["\\A"] = sig_t.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_t[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } @@ -111,13 +96,13 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == "$xnor") gate_type = "$_XOR_"; log_assert(!gate_type.empty()); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_b.chunks().at(i); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_b[i]; + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } @@ -125,8 +110,6 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); if (sig_y.size() == 0) @@ -159,21 +142,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) while (sig_a.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2); - sig_t.expand(); for (int i = 0; i < sig_a.size(); i += 2) { if (i+1 == sig_a.size()) { - sig_t.append(sig_a.chunks().at(i)); + sig_t.append(sig_a[i]); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_a.chunks().at(i+1); - gate->connections["\\Y"] = sig_t.chunks().at(i/2); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_a[i+1]; + gate->connections["\\Y"] = sig_t[i/2]; last_output = &gate->connections["\\Y"]; module->add(gate); } @@ -202,26 +184,23 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig) { - sig.expand(); - while (sig.size() > 1) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2); - sig_t.expand(); for (int i = 0; i < sig.size(); i += 2) { if (i+1 == sig.size()) { - sig_t.append(sig.chunks().at(i)); + sig_t.append(sig[i]); continue; } RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_OR_"; - gate->connections["\\A"] = sig.chunks().at(i); - gate->connections["\\B"] = sig.chunks().at(i+1); - gate->connections["\\Y"] = sig_t.chunks().at(i/2); + gate->connections["\\A"] = sig[i]; + gate->connections["\\B"] = sig[i+1]; + gate->connections["\\Y"] = sig_t[i/2]; module->add(gate); } @@ -289,25 +268,18 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) { - int width = cell->parameters.at("\\WIDTH").as_int(); - RTLIL::SigSpec sig_a = cell->connections.at("\\A"); - sig_a.expand(); - RTLIL::SigSpec sig_b = cell->connections.at("\\B"); - sig_b.expand(); - RTLIL::SigSpec sig_y = cell->connections.at("\\Y"); - sig_y.expand(); - for (int i = 0; i < width; i++) { + for (int i = 0; i < SIZE(sig_y); i++) { RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = "$_MUX_"; - gate->connections["\\A"] = sig_a.chunks().at(i); - gate->connections["\\B"] = sig_b.chunks().at(i); + gate->connections["\\A"] = sig_a[i]; + gate->connections["\\B"] = sig_b[i]; gate->connections["\\S"] = cell->connections.at("\\S"); - gate->connections["\\Y"] = sig_y.chunks().at(i); + gate->connections["\\Y"] = sig_y[i]; module->add(gate); } } @@ -335,13 +307,8 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - sig_s.expand(); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - sig_r.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol); @@ -349,9 +316,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::Cell *gate = new RTLIL::Cell; gate->name = NEW_ID; gate->type = gate_type; - gate->connections["\\S"] = sig_s.chunks().at(i); - gate->connections["\\R"] = sig_r.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\S"] = sig_s[i]; + gate->connections["\\R"] = sig_r[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -362,12 +329,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DFF_%c_", clk_pol); @@ -376,8 +339,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -390,18 +353,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); - RTLIL::SigSpec sig_s = cell->connections.at("\\SET"); - sig_s.expand(); - RTLIL::SigSpec sig_r = cell->connections.at("\\CLR"); - sig_r.expand(); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol); @@ -410,10 +365,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\C"] = sig_clk; - gate->connections["\\S"] = sig_s.chunks().at(i); - gate->connections["\\R"] = sig_r.chunks().at(i); - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\S"] = sig_s[i]; + gate->connections["\\R"] = sig_r[i]; + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -430,12 +385,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_clk = cell->connections.at("\\CLK"); RTLIL::SigSpec sig_rst = cell->connections.at("\\ARST"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol); std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol); @@ -446,8 +397,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell) gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0; gate->connections["\\C"] = sig_clk; gate->connections["\\R"] = sig_rst; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } @@ -458,12 +409,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N'; RTLIL::SigSpec sig_en = cell->connections.at("\\EN"); - RTLIL::SigSpec sig_d = cell->connections.at("\\D"); - sig_d.expand(); - RTLIL::SigSpec sig_q = cell->connections.at("\\Q"); - sig_q.expand(); std::string gate_type = stringf("$_DLATCH_%c_", en_pol); @@ -472,8 +419,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell) gate->name = NEW_ID; gate->type = gate_type; gate->connections["\\E"] = sig_en; - gate->connections["\\D"] = sig_d.chunks().at(i); - gate->connections["\\Q"] = sig_q.chunks().at(i); + gate->connections["\\D"] = sig_d[i]; + gate->connections["\\Q"] = sig_q[i]; module->add(gate); } } |