diff options
114 files changed, 2332 insertions, 2871 deletions
@@ -62,7 +62,6 @@ Yosys 0.9 .. Yosys 0.9-dev - Improved support of $readmem[hb] Memory Content File inclusion - Added "opt_lut_ins" pass - Added "logger" pass - - Removed "dffsr2dff" (use opt_rmdff instead) - Added "design -delete" - Added "select -unset" - Use YosysHQ/abc instead of upstream berkeley-abc/abc @@ -70,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells - Added "dfflegalize" pass - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass + - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass Yosys 0.8 .. Yosys 0.9 ---------------------- @@ -82,7 +82,7 @@ all: top-all YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) -CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include +CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include LDLIBS := $(LDLIBS) -lstdc++ -lm PLUGIN_LDFLAGS := @@ -123,7 +123,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.9+3468 +YOSYS_VER := 0.9+3568 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o @@ -593,7 +593,7 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) -$(eval $(call add_include_file,backends/ilang/ilang_backend.h)) +$(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc)) @@ -634,7 +634,7 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc else include $(YOSYS_SRC)/frontends/verilog/Makefile.inc -include $(YOSYS_SRC)/frontends/ilang/Makefile.inc +include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc include $(YOSYS_SRC)/frontends/ast/Makefile.inc include $(YOSYS_SRC)/frontends/blif/Makefile.inc @@ -651,7 +651,7 @@ include $(YOSYS_SRC)/passes/opt/Makefile.inc include $(YOSYS_SRC)/passes/techmap/Makefile.inc include $(YOSYS_SRC)/backends/verilog/Makefile.inc -include $(YOSYS_SRC)/backends/ilang/Makefile.inc +include $(YOSYS_SRC)/backends/rtlil/Makefile.inc include $(YOSYS_SRC)/techlibs/common/Makefile.inc diff --git a/backends/btor/.gitignore b/backends/btor/.gitignore new file mode 100644 index 000000000..d23d492d7 --- /dev/null +++ b/backends/btor/.gitignore @@ -0,0 +1 @@ +/test_cells.tmp/ diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index e5da6c1e7..5abab8978 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -205,9 +205,8 @@ struct BtorWorker if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor"; log_assert(!btor_op.empty()); - int width = GetSize(cell->getPort(ID::Y)); - width = std::max(width, GetSize(cell->getPort(ID::A))); - width = std::max(width, GetSize(cell->getPort(ID::B))); + int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y))); + int width = std::max(width_ay, GetSize(cell->getPort(ID::B))); bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false; @@ -224,11 +223,23 @@ struct BtorWorker int sid = get_bv_sid(width); int nid; + int nid_a; + if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) { + // sign-extend A up to the width of Y + int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed); + + // zero-extend the rest + int zeroes = get_sig_nid(Const(0, width-width_ay)); + nid_a = next_nid++; + btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded); + } else { + nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); + } + + int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); + if (btor_op == "shift") { - int nid_a = get_sig_nid(cell->getPort(ID::A), width, false); - int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); - int nid_r = next_nid++; btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b); @@ -248,9 +259,6 @@ struct BtorWorker } else { - int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); - int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); - nid = next_nid++; btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); } diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh index 3f077201a..0a011932d 100644..100755 --- a/backends/btor/test_cells.sh +++ b/backends/btor/test_cells.sh @@ -6,7 +6,7 @@ rm -rf test_cells.tmp mkdir -p test_cells.tmp cd test_cells.tmp -../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod /$divfloor /$modfloor' +../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod /$divfloor /$modfloor /$shiftx' for fn in test_*.il; do ../../../yosys -p " @@ -19,7 +19,7 @@ for fn in test_*.il; do hierarchy -top main write_btor ${fn%.il}.btor " - boolectormc -kmax 1 --trace-gen --stop-first -v ${fn%.il}.btor > ${fn%.il}.out + btormc -kmax 1 --trace-gen --stop-first -v ${fn%.il}.btor > ${fn%.il}.out if grep " SATISFIABLE" ${fn%.il}.out; then echo "Check failed for ${fn%.il}." exit 1 diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index f0d7b9fc7..41089a153 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -452,10 +452,11 @@ struct value : public expr_base<value<Bits>> { bool carry = CarryIn; for (size_t n = 0; n < result.chunks; n++) { result.data[n] = data[n] + (Invert ? ~other.data[n] : other.data[n]) + carry; + if (result.chunks - 1 == n) + result.data[result.chunks - 1] &= result.msb_mask; carry = (result.data[n] < data[n]) || (result.data[n] == data[n] && carry); } - result.data[result.chunks - 1] &= result.msb_mask; return {result, carry}; } @@ -823,6 +824,7 @@ struct debug_alias {}; // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used // in the C API, or it would not be possible to cast between the pointers to these. struct debug_item : ::cxxrtl_object { + // Object types. enum : uint32_t { VALUE = CXXRTL_VALUE, WIRE = CXXRTL_WIRE, @@ -830,13 +832,24 @@ struct debug_item : ::cxxrtl_object { ALIAS = CXXRTL_ALIAS, }; + // Object flags. + enum : uint32_t { + INPUT = CXXRTL_INPUT, + OUTPUT = CXXRTL_OUTPUT, + INOUT = CXXRTL_INOUT, + DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC, + DRIVEN_COMB = CXXRTL_DRIVEN_COMB, + UNDRIVEN = CXXRTL_UNDRIVEN, + }; + debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {} template<size_t Bits> - debug_item(value<Bits> &item, size_t lsb_offset = 0) { + debug_item(value<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) { static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), "value<Bits> is not compatible with C layout"); type = VALUE; + flags = flags_; width = Bits; lsb_at = lsb_offset; depth = 1; @@ -850,6 +863,7 @@ struct debug_item : ::cxxrtl_object { static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), "value<Bits> is not compatible with C layout"); type = VALUE; + flags = DRIVEN_COMB; width = Bits; lsb_at = lsb_offset; depth = 1; @@ -859,11 +873,12 @@ struct debug_item : ::cxxrtl_object { } template<size_t Bits> - debug_item(wire<Bits> &item, size_t lsb_offset = 0) { + debug_item(wire<Bits> &item, size_t lsb_offset = 0, uint32_t flags_ = 0) { static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) && sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t), "wire<Bits> is not compatible with C layout"); type = WIRE; + flags = flags_; width = Bits; lsb_at = lsb_offset; depth = 1; @@ -877,6 +892,7 @@ struct debug_item : ::cxxrtl_object { static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t), "memory<Width> is not compatible with C layout"); type = MEMORY; + flags = 0; width = Width; lsb_at = 0; depth = item.data.size(); @@ -890,6 +906,7 @@ struct debug_item : ::cxxrtl_object { static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), "value<Bits> is not compatible with C layout"); type = ALIAS; + flags = DRIVEN_COMB; width = Bits; lsb_at = lsb_offset; depth = 1; @@ -904,6 +921,7 @@ struct debug_item : ::cxxrtl_object { sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t), "wire<Bits> is not compatible with C layout"); type = ALIAS; + flags = DRIVEN_COMB; width = Bits; lsb_at = lsb_offset; depth = 1; diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 6d3c2f4f9..dfea04409 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -200,16 +200,12 @@ bool is_elidable_cell(RTLIL::IdString type) ID($mux), ID($concat), ID($slice), ID($pmux)); } -bool is_sync_ff_cell(RTLIL::IdString type) -{ - return type.in( - ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce)); -} - bool is_ff_cell(RTLIL::IdString type) { - return is_sync_ff_cell(type) || type.in( - ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr)); + return type.in( + ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), + ID($adff), ID($adffe), ID($dffsr), ID($dffsre), + ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr)); } bool is_internal_cell(RTLIL::IdString type) @@ -277,6 +273,7 @@ struct FlowGraph { std::vector<Node*> nodes; dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses; dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable; + dict<RTLIL::SigBit, bool> bit_has_state; ~FlowGraph() { @@ -284,17 +281,24 @@ struct FlowGraph { delete node; } - void add_defs(Node *node, const RTLIL::SigSpec &sig, bool fully_sync, bool elidable) + void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool elidable) { for (auto chunk : sig.chunks()) if (chunk.wire) { - if (fully_sync) + if (is_ff) { + // A sync def means that a wire holds design state because it is driven directly by + // a flip-flop output. Such a wire can never be unbuffered. wire_sync_defs[chunk.wire].insert(node); - else + } else { + // A comb def means that a wire doesn't hold design state. It might still be connected, + // indirectly, to a flip-flop output. wire_comb_defs[chunk.wire].insert(node); + } } + for (auto bit : sig.bits()) + bit_has_state[bit] |= is_ff; // Only comb defs of an entire wire in the right order can be elided. - if (!fully_sync && sig.is_wire()) + if (!is_ff && sig.is_wire()) wire_def_elidable[sig.as_wire()] = elidable; } @@ -322,7 +326,7 @@ struct FlowGraph { // Connections void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn) { - add_defs(node, conn.first, /*fully_sync=*/false, /*elidable=*/true); + add_defs(node, conn.first, /*is_ff=*/false, /*elidable=*/true); add_uses(node, conn.second); } @@ -369,7 +373,7 @@ struct FlowGraph { if (cell->output(conn.first)) if (is_cxxrtl_sync_port(cell, conn.first)) { // See note regarding elidability below. - add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); } } @@ -378,18 +382,18 @@ struct FlowGraph { for (auto conn : cell->connections()) { if (cell->output(conn.first)) { if (is_elidable_cell(cell->type)) - add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/true); - else if (is_sync_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool())) - add_defs(node, conn.second, /*fully_sync=*/true, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/true); + else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool())) + add_defs(node, conn.second, /*is_ff=*/true, /*elidable=*/false); else if (is_internal_cell(cell->type)) - add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); else if (!is_cxxrtl_sync_port(cell, conn.first)) { // Although at first it looks like outputs of user-defined cells may always be elided, the reality is // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb // outputs are assigned in a different way depending on whether the cell's eval() immediately converged. // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify // the infrastructure required to elide outputs of cells with many of them. - add_defs(node, conn.second, /*fully_sync=*/false, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); } } if (cell->input(conn.first)) @@ -427,7 +431,7 @@ struct FlowGraph { void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_) { for (auto &action : case_->actions) { - add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false); add_uses(node, action.second); } for (auto sub_switch : case_->switches) { @@ -446,9 +450,9 @@ struct FlowGraph { for (auto sync : process->syncs) for (auto action : sync->actions) { if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe) - add_defs(node, action.first, /*is_sync=*/true, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/true, /*elidable=*/false); else - add_defs(node, action.first, /*is_sync=*/false, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false); add_uses(node, action.second); } } @@ -549,6 +553,7 @@ struct CxxrtlWorker { pool<const RTLIL::Wire*> localized_wires; dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires; dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires; + dict<RTLIL::SigBit, bool> bit_has_state; dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations; dict<const RTLIL::Module*, bool> eval_converges; @@ -1142,7 +1147,7 @@ struct CxxrtlWorker { } // The generated code has two bounds checks; one in an assertion, and another that guards the read. // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless - // loudly crashes if an illegal condition is encountered. The assert may be turned off with -NDEBUG not + // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DNDEBUG not // just for release builds, but also to make sure the simulator (which is presumably embedded in some // larger program) will never crash the code that calls into it. // @@ -1635,6 +1640,10 @@ struct CxxrtlWorker { size_t count_alias_wires = 0; size_t count_member_wires = 0; size_t count_skipped_wires = 0; + size_t count_driven_sync = 0; + size_t count_driven_comb = 0; + size_t count_undriven = 0; + size_t count_mixed_driver = 0; inc_indent(); f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n"; for (auto wire : module->wires()) { @@ -1660,9 +1669,55 @@ struct CxxrtlWorker { count_alias_wires++; } else if (!localized_wires.count(wire)) { // Member wire + std::vector<std::string> flags; + + if (wire->port_input && wire->port_output) + flags.push_back("INOUT"); + else if (wire->port_input) + flags.push_back("INPUT"); + else if (wire->port_output) + flags.push_back("OUTPUT"); + + bool has_driven_sync = false; + bool has_driven_comb = false; + bool has_undriven = false; + SigSpec sig(wire); + for (auto bit : sig.bits()) + if (!bit_has_state.count(bit)) + has_undriven = true; + else if (bit_has_state[bit]) + has_driven_sync = true; + else + has_driven_comb = true; + if (has_driven_sync) + flags.push_back("DRIVEN_SYNC"); + if (has_driven_sync && !has_driven_comb && !has_undriven) + count_driven_sync++; + if (has_driven_comb) + flags.push_back("DRIVEN_COMB"); + if (!has_driven_sync && has_driven_comb && !has_undriven) + count_driven_comb++; + if (has_undriven) + flags.push_back("UNDRIVEN"); + if (!has_driven_sync && !has_driven_comb && has_undriven) + count_undriven++; + if (has_driven_sync + has_driven_comb + has_undriven > 1) + count_mixed_driver++; + f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); f << ", debug_item(" << mangle(wire) << ", "; - f << wire->start_offset << "));\n"; + f << wire->start_offset; + bool first = true; + for (auto flag : flags) { + if (first) { + first = false; + f << ", "; + } else { + f << "|"; + } + f << "debug_item::" << flag; + } + f << "));\n"; count_member_wires++; } else { count_skipped_wires++; @@ -1690,7 +1745,11 @@ struct CxxrtlWorker { log_debug(" Public wires: %zu, of which:\n", count_public_wires); log_debug(" Const wires: %zu\n", count_const_wires); log_debug(" Alias wires: %zu\n", count_alias_wires); - log_debug(" Member wires: %zu\n", count_member_wires); + log_debug(" Member wires: %zu, of which:\n", count_member_wires); + log_debug(" Driven sync: %zu\n", count_driven_sync); + log_debug(" Driven comb: %zu\n", count_driven_comb); + log_debug(" Undriven: %zu\n", count_undriven); + log_debug(" Mixed driver: %zu\n", count_mixed_driver); log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires); } @@ -2209,6 +2268,9 @@ struct CxxrtlWorker { eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty(); + for (auto item : flow.bit_has_state) + bit_has_state.insert(item); + if (debug_info) { // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these // at essentially zero additional cost. diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h index 1f1942803..385d6dcf3 100644 --- a/backends/cxxrtl/cxxrtl_capi.h +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -73,6 +73,10 @@ int cxxrtl_commit(cxxrtl_handle handle); size_t cxxrtl_step(cxxrtl_handle handle); // Type of a simulated object. +// +// The type of a simulated object indicates the way it is stored and the operations that are legal +// to perform on it (i.e. won't crash the simulation). It says very little about object semantics, +// which is specified through flags. enum cxxrtl_type { // Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by // combinatorial cells, or toplevel input nodes. @@ -86,7 +90,8 @@ enum cxxrtl_type { CXXRTL_VALUE = 0, // Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by - // storage cells, or by combinatorial cells that are a part of a feedback path. + // storage cells, or by combinatorial cells that are a part of a feedback path. They are also + // present in non-optimized builds. // // Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are // distinct for wires). Note that changes to the bits driven by combinatorial cells will be @@ -103,7 +108,7 @@ enum cxxrtl_type { CXXRTL_MEMORY = 2, // Aliases correspond to netlist nodes driven by another node such that their value is always - // exactly equal, or driven by a constant value. + // exactly equal. // // Aliases can be inspected via the `curr` pointer. They cannot be modified, and the `next` // pointer is always NULL. @@ -112,6 +117,66 @@ enum cxxrtl_type { // More object types may be added in the future, but the existing ones will never change. }; +// Flags of a simulated object. +// +// The flags of a simulated object indicate its role in the netlist: +// * The flags `CXXRTL_INPUT` and `CXXRTL_OUTPUT` designate module ports. +// * The flags `CXXRTL_DRIVEN_SYNC`, `CXXRTL_DRIVEN_COMB`, and `CXXRTL_UNDRIVEN` specify +// the semantics of node state. An object with several of these flags set has different bits +// follow different semantics. +enum cxxrtl_flag { + // Node is a module input port. + // + // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined + // with `CXXRTL_OUTPUT`, as well as other flags. + CXXRTL_INPUT = 1 << 0, + + // Node is a module output port. + // + // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with `CXXRTL_INPUT`, + // as well as other flags. + CXXRTL_OUTPUT = 1 << 1, + + // Node is a module inout port. + // + // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with other flags. + CXXRTL_INOUT = (CXXRTL_INPUT|CXXRTL_OUTPUT), + + // Node has bits that are driven by a storage cell. + // + // This flag can be set on objects of type `CXXRTL_WIRE`. It may be combined with + // `CXXRTL_DRIVEN_COMB` and `CXXRTL_UNDRIVEN`, as well as other flags. + // + // This flag is set on wires that have bits connected directly to the output of a flip-flop or + // a latch, and hold its state. Many `CXXRTL_WIRE` objects may not have the `CXXRTL_DRIVEN_SYNC` + // flag set; for example, output ports and feedback wires generally won't. Writing to the `next` + // pointer of these wires updates stored state, and for designs without combinatorial loops, + // capturing the value from every of these wires through the `curr` pointer creates a complete + // snapshot of the design state. + CXXRTL_DRIVEN_SYNC = 1 << 2, + + // Node has bits that are driven by a combinatorial cell or another node. + // + // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined + // with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags. + // + // This flag is set on objects that have bits connected to the output of a combinatorial cell, + // or directly to another node. For designs without combinatorial loops, writing to such bits + // through the `next` pointer (if it is not NULL) has no effect. + CXXRTL_DRIVEN_COMB = 1 << 3, + + // Node has bits that are not driven. + // + // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined + // with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_DRIVEN_COMB`, as well as other flags. + // + // This flag is set on objects that have bits not driven by an output of any cell or by another + // node, such as inputs and dangling wires. + CXXRTL_UNDRIVEN = 1 << 4, + + // More object flags may be added in the future, but the existing ones will never change. +}; + // Description of a simulated object. // // The `data` array can be accessed directly to inspect and, if applicable, modify the bits @@ -123,6 +188,9 @@ struct cxxrtl_object { // determines all other properties of the object. uint32_t type; // actually `enum cxxrtl_type` + // Flags of the object. + uint32_t flags; // actually bit mask of `enum cxxrtl_flags` + // Width of the object in bits. size_t width; diff --git a/backends/ilang/Makefile.inc b/backends/ilang/Makefile.inc deleted file mode 100644 index 52fc2b891..000000000 --- a/backends/ilang/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ - -OBJS += backends/ilang/ilang_backend.o - diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 98a14173b..a6b36de6c 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -59,7 +59,7 @@ struct IntersynthBackend : public Backend { log(" do not generate celltypes and conntypes commands. i.e. just output\n"); log(" the netlists. this is used for postsilicon synthesis.\n"); log("\n"); - log(" -lib <verilog_or_ilang_file>\n"); + log(" -lib <verilog_or_rtlil_file>\n"); log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); @@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); } diff --git a/backends/rtlil/Makefile.inc b/backends/rtlil/Makefile.inc new file mode 100644 index 000000000..f691282ca --- /dev/null +++ b/backends/rtlil/Makefile.inc @@ -0,0 +1,3 @@ + +OBJS += backends/rtlil/rtlil_backend.o + diff --git a/backends/ilang/ilang_backend.cc b/backends/rtlil/rtlil_backend.cc index aa5a175ca..01b4bde53 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -18,19 +18,19 @@ * --- * * A very simple and straightforward backend for the RTLIL text - * representation (as understood by the 'ilang' frontend). + * representation. * */ -#include "ilang_backend.h" +#include "rtlil_backend.h" #include "kernel/yosys.h" #include <errno.h> USING_YOSYS_NAMESPACE -using namespace ILANG_BACKEND; +using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN -void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) +void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) width = data.bits.size() - offset; @@ -83,7 +83,7 @@ void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi } } -void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint) +void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, autoint); @@ -97,7 +97,7 @@ void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, } } -void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint) +void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint) { if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk(), autoint); @@ -111,7 +111,7 @@ void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo } } -void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) +void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { for (auto &it : wire->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -136,7 +136,7 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s\n", wire->name.c_str()); } -void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) +void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { for (auto &it : memory->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -153,7 +153,7 @@ void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL f << stringf("%s\n", memory->name.c_str()); } -void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) +void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { for (auto &it : cell->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -177,7 +177,7 @@ void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) +void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) { @@ -192,7 +192,7 @@ void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, con dump_proc_switch(f, indent, *it); } -void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) +void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); @@ -225,7 +225,7 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy) +void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy) { f << stringf("%s" "sync ", indent.c_str()); switch (sy->type) { @@ -251,7 +251,7 @@ void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT } } -void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) +void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); @@ -265,7 +265,7 @@ void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) +void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { f << stringf("%s" "connect ", indent.c_str()); dump_sigspec(f, left); @@ -274,7 +274,7 @@ void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } -void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { bool print_header = flag_m || design->selected_whole_module(module->name); bool print_body = !flag_n || !design->selected_whole_module(module->name); @@ -360,7 +360,7 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { int init_autoidx = autoidx; @@ -396,15 +396,15 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN -struct IlangBackend : public Backend { - IlangBackend() : Backend("ilang", "write design to ilang file") { } +struct RTLILBackend : public Backend { + RTLILBackend() : Backend("rtlil", "write design to RTLIL file") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" write_ilang [filename]\n"); + log(" write_rtlil [filename]\n"); log("\n"); - log("Write the current design to an 'ilang' file. (ilang is a text representation\n"); + log("Write the current design to an RTLIL file. (RTLIL is a text representation\n"); log("of a design in yosys's internal format.)\n"); log("\n"); log(" -selected\n"); @@ -415,7 +415,7 @@ struct IlangBackend : public Backend { { bool selected = false; - log_header(design, "Executing ILANG backend.\n"); + log_header(design, "Executing RTLIL backend.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -432,12 +432,27 @@ struct IlangBackend : public Backend { log("Output filename: %s\n", filename.c_str()); *f << stringf("# Generated by %s\n", yosys_version_str); - ILANG_BACKEND::dump_design(*f, design, selected, true, false); + RTLIL_BACKEND::dump_design(*f, design, selected, true, false); + } +} RTLILBackend; + +struct IlangBackend : public Backend { + IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log("See `help write_rtlil`.\n"); + log("\n"); + } + void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override + { + RTLILBackend.execute(f, filename, args, design); } } IlangBackend; struct DumpPass : public Pass { - DumpPass() : Pass("dump", "print parts of the design in ilang format") { } + DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -445,7 +460,7 @@ struct DumpPass : public Pass { log(" dump [options] [selection]\n"); log("\n"); log("Write the selected parts of the design to the console or specified file in\n"); - log("ilang format.\n"); + log("RTLIL format.\n"); log("\n"); log(" -m\n"); log(" also dump the module headers, even if only parts of a single\n"); @@ -508,7 +523,7 @@ struct DumpPass : public Pass { f = &buf; } - ILANG_BACKEND::dump_design(*f, design, true, flag_m, flag_n); + RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n); if (!filename.empty()) { delete f; diff --git a/backends/ilang/ilang_backend.h b/backends/rtlil/rtlil_backend.h index 97dcbb628..77eea353c 100644 --- a/backends/ilang/ilang_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -18,19 +18,19 @@ * --- * * A very simple and straightforward backend for the RTLIL text - * representation (as understood by the 'ilang' frontend). + * representation. * */ -#ifndef ILANG_BACKEND_H -#define ILANG_BACKEND_H +#ifndef RTLIL_BACKEND_H +#define RTLIL_BACKEND_H #include "kernel/yosys.h" #include <stdio.h> YOSYS_NAMESPACE_BEGIN -namespace ILANG_BACKEND { +namespace RTLIL_BACKEND { void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index a79c0bd99..4a53ce6d5 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -824,38 +824,49 @@ struct Smt2Worker is_register = true; if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) { RTLIL::SigSpec sig = sigmap(wire); + std::vector<std::string> comments; if (wire->port_input) - decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); if (wire->port_output) - decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); if (is_register) - decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) - decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig))) - decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), + comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : "")); if (bvmode && GetSize(sig) > 1) { + std::string sig_bv = get_bv(sig); + if (!comments.empty()) + decls.insert(decls.end(), comments.begin(), comments.end()); decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n", - get_id(module), get_id(wire), get_id(module), GetSize(sig), get_bv(sig).c_str())); + get_id(module), get_id(wire), get_id(module), GetSize(sig), sig_bv.c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))", get_id(module), get_id(wire), get_id(module), get_id(wire))); } else { - for (int i = 0; i < GetSize(sig); i++) + std::vector<std::string> sig_bool; + for (int i = 0; i < GetSize(sig); i++) { + sig_bool.push_back(get_bool(sig[i])); + } + if (!comments.empty()) + decls.insert(decls.end(), comments.begin(), comments.end()); + for (int i = 0; i < GetSize(sig); i++) { if (GetSize(sig) > 1) { decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n", - get_id(module), get_id(wire), i, get_id(module), get_bool(sig[i]).c_str())); + get_id(module), get_id(wire), i, get_id(module), sig_bool[i].c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))", get_id(module), get_id(wire), i, get_id(module), get_id(wire), i)); } else { decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n", - get_id(module), get_id(wire), get_id(module), get_bool(sig[i]).c_str())); + get_id(module), get_id(wire), get_id(module), sig_bool[i].c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))", get_id(module), get_id(wire), get_id(module), get_id(wire))); } + } } } } @@ -1392,7 +1403,7 @@ struct Smt2Backend : public Backend { log(" the given option as a `(set-option ...)` command in the SMT-LIBv2.\n"); log("\n"); log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n"); - log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n"); + log("R. Cok's tutorial: https://smtlib.github.io/jSMTLIB/SMTLIBTutorial.pdf\n"); log("\n"); log("---------------------------------------------------------------------------\n"); log("\n"); diff --git a/backends/smv/.gitignore b/backends/smv/.gitignore new file mode 100644 index 000000000..d23d492d7 --- /dev/null +++ b/backends/smv/.gitignore @@ -0,0 +1 @@ +/test_cells.tmp/ diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a0e677d13..372f68ea5 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -750,21 +750,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = "); if (cell->getParam(ID::B_SIGNED).as_bool()) { - f << stringf("$signed("); - dump_sigspec(f, cell->getPort(ID::B)); - f << stringf(")"); + dump_cell_expr_port(f, cell, "B", true); f << stringf(" < 0 ? "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" << - "); dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); dump_sigspec(f, cell->getPort(ID::B)); } else { - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); dump_sigspec(f, cell->getPort(ID::B)); } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 9a5aa15f9..203b50021 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -250,7 +250,7 @@ namespace AST // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init); - void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map); + void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope = true); void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules); void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places, dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a166f8a89..153a42e19 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -89,7 +89,7 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg case 'S': case 'd': case 'D': - if (got_len) + if (got_len && len_value != 0) goto unsupported_format; YS_FALLTHROUGH case 'x': @@ -110,6 +110,12 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg goto unsupported_format; break; + case 'l': + case 'L': + if (got_len) + goto unsupported_format; + break; + default: unsupported_format: log_file_error(filename, location.first_line, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); @@ -155,6 +161,11 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg sout += log_id(current_module->name); break; + case 'l': + case 'L': + sout += log_id(current_module->name); + break; + default: log_abort(); } @@ -380,31 +391,66 @@ static int size_packed_struct(AstNode *snode, int base_offset) static AstNode *node_int(int ival) { - // maybe mkconst_int should have default values for the common integer case - return AstNode::mkconst_int(ival, true, 32); + return AstNode::mkconst_int(ival, true); +} + +static AstNode *multiply_by_const(AstNode *expr_node, int stride) +{ + return new AstNode(AST_MUL, expr_node, node_int(stride)); } -static AstNode *offset_indexed_range(int offset_right, int stride, AstNode *left_expr, AstNode *right_expr) +static AstNode *offset_indexed_range(int offset, int stride, AstNode *left_expr, AstNode *right_expr) { // adjust the range expressions to add an offset into the struct // and maybe index using an array stride auto left = left_expr->clone(); auto right = right_expr->clone(); - if (stride == 1) { - // just add the offset - left = new AstNode(AST_ADD, node_int(offset_right), left); - right = new AstNode(AST_ADD, node_int(offset_right), right); + if (stride > 1) { + // newleft = (left + 1) * stride - 1 + left = new AstNode(AST_SUB, multiply_by_const(new AstNode(AST_ADD, left, node_int(1)), stride), node_int(1)); + // newright = right * stride + right = multiply_by_const(right, stride); + } + // add the offset + if (offset) { + left = new AstNode(AST_ADD, node_int(offset), left); + right = new AstNode(AST_ADD, node_int(offset), right); + } + return new AstNode(AST_RANGE, left, right); +} + +static AstNode *make_struct_index_range(AstNode *node, AstNode *rnode, int stride, int offset) +{ + // generate a range node to perform either bit or array indexing + if (rnode->children.size() == 1) { + // index e.g. s.a[i] + return offset_indexed_range(offset, stride, rnode->children[0], rnode->children[0]); + } + else if (rnode->children.size() == 2) { + // slice e.g. s.a[i:j] + return offset_indexed_range(offset, stride, rnode->children[0], rnode->children[1]); } else { - // newleft = offset_right - 1 + (left + 1) * stride - left = new AstNode(AST_ADD, new AstNode(AST_SUB, node_int(offset_right), node_int(1)), - new AstNode(AST_MUL, node_int(stride), new AstNode(AST_ADD, left, node_int(1)))); - // newright = offset_right + right * stride - right = new AstNode(AST_ADD, node_int(offset_right), new AstNode(AST_MUL, right, node_int(stride))); + struct_op_error(node); } +} + +static AstNode *slice_range(AstNode *rnode, AstNode *snode) +{ + // apply the bit slice indicated by snode to the range rnode + log_assert(rnode->type==AST_RANGE); + auto left = rnode->children[0]; + auto right = rnode->children[1]; + log_assert(snode->type==AST_RANGE); + auto slice_left = snode->children[0]; + auto slice_right = snode->children[1]; + auto width = new AstNode(AST_SUB, slice_left->clone(), slice_right->clone()); + right = new AstNode(AST_ADD, right->clone(), slice_right->clone()); + left = new AstNode(AST_ADD, right->clone(), width); return new AstNode(AST_RANGE, left, right); } + static AstNode *make_struct_member_range(AstNode *node, AstNode *member_node) { // Work out the range in the packed array that corresponds to a struct member @@ -414,27 +460,26 @@ static AstNode *make_struct_member_range(AstNode *node, AstNode *member_node) int range_right = member_node->range_right; if (node->children.empty()) { // no range operations apply, return the whole width + return make_range(range_left, range_right); } - else if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { - auto rnode = node->children[0]; - int stride = get_struct_array_width(member_node); - if (rnode->children.size() == 1) { - // index e.g. s.a[i] - return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[0]); - } - else if (rnode->children.size() == 2) { - // slice e.g. s.a[i:j] - return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[1]); - } - else { - struct_op_error(node); - } + int stride = get_struct_array_width(member_node); + if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + // bit or array indexing e.g. s.a[2] or s.a[1:0] + return make_struct_index_range(node, node->children[0], stride, range_right); + } + else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) { + // multirange, i.e. bit slice after array index, e.g. s.a[i][p:q] + log_assert(stride > 1); + auto mrnode = node->children[0]; + auto element_range = make_struct_index_range(node, mrnode->children[0], stride, range_right); + // then apply bit slice range + auto range = slice_range(element_range, mrnode->children[1]); + delete element_range; + return range; } else { - // TODO multirange, i.e. bit slice after array index s.a[i][p:q] struct_op_error(node); } - return make_range(range_left, range_right); } static void add_members_to_scope(AstNode *snode, std::string name) @@ -1563,6 +1608,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_IDENTIFIER) { if (current_scope.count(str) == 0) { AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; + const std::string& mod_scope = current_scope_ast->str; + if (str[0] == '\\' && str.substr(0, mod_scope.size()) == mod_scope) { + std::string new_str = "\\" + str.substr(mod_scope.size() + 1); + if (current_scope.count(new_str)) { + str = new_str; + } + } for (auto node : current_scope_ast->children) { //log("looking at mod scope child %s\n", type2str(node->type).c_str()); switch (node->type) { @@ -1807,7 +1859,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -1883,7 +1935,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < children.size(); i++) { - children[i]->simplify(false, false, false, stage, -1, false, false); + children[i]->simplify(const_fold, false, false, stage, -1, false, false); current_ast_mod->children.push_back(children[i]); } @@ -1920,7 +1972,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -1999,7 +2051,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(false, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -3052,7 +3104,7 @@ skip_dynamic_range_lvalue_expansion:; bool all_args_const = true; for (auto child : children) { while (child->simplify(true, false, false, 1, -1, false, true)) { } - if (child->type != AST_CONSTANT) + if (child->type != AST_CONSTANT && child->type != AST_REALVALUE) all_args_const = false; } @@ -3177,14 +3229,15 @@ skip_dynamic_range_lvalue_expansion:; if (wire_cache.count(child->str)) { wire = wire_cache.at(child->str); - if (wire->children.empty()) { + bool contains_value = wire->type == AST_LOCALPARAM; + if (wire->children.size() == contains_value) { for (auto c : child->children) wire->children.push_back(c->clone()); } else if (!child->children.empty()) { while (child->simplify(true, false, false, stage, -1, false, false)) { } - if (GetSize(child->children) == GetSize(wire->children)) { + if (GetSize(child->children) == GetSize(wire->children) - contains_value) { for (int i = 0; i < GetSize(child->children); i++) - if (*child->children.at(i) != *wire->children.at(i)) + if (*child->children.at(i) != *wire->children.at(i + contains_value)) goto tcall_incompatible_wires; } else { tcall_incompatible_wires: @@ -3711,8 +3764,11 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m } // annotate the names of all wires and other named objects in a generate block -void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map) +void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope) { + // `original_scope` defaults to false, and is used to prevent the premature + // prefixing of items in named sub-blocks + if (!index_var.empty() && type == AST_IDENTIFIER && str == index_var) { if (children.empty()) { current_scope[index_var]->children[0]->cloneInto(this); @@ -3725,53 +3781,85 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma } } - if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) && name_map.count(str) > 0) - str = name_map[str]; + if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) { + if (name_map.count(str) > 0) { + str = name_map[str]; + } else { + // remap the prefix of this ident if it is a local generate scope + size_t pos = str.rfind('.'); + if (pos != std::string::npos) { + std::string existing_prefix = str.substr(0, pos); + if (name_map.count(existing_prefix) > 0) { + str = name_map[existing_prefix] + str.substr(pos); + } + } + } + } std::map<std::string, std::string> backup_name_map; + auto prefix_node = [&](AstNode* child) { + if (backup_name_map.size() == 0) + backup_name_map = name_map; + + // if within a nested scope + if (!original_scope) { + // this declaration shadows anything in the parent scope(s) + name_map[child->str] = child->str; + return; + } + + std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; + size_t pos = child->str.rfind('.'); + if (pos == std::string::npos) + pos = child->str[0] == '\\' && prefix[0] == '\\' ? 1 : 0; + else + pos = pos + 1; + new_name = child->str.substr(0, pos) + new_name + child->str.substr(pos); + if (new_name[0] != '$' && new_name[0] != '\\') + new_name = prefix[0] + new_name; + + name_map[child->str] = new_name; + if (child->type == AST_FUNCTION) + replace_result_wire_name_in_function(child, child->str, new_name); + else + child->str = new_name; + current_scope[new_name] = child; + }; + for (size_t i = 0; i < children.size(); i++) { AstNode *child = children[i]; - if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || - child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL || child->type == AST_TYPEDEF || child->type == AST_ENUM_ITEM) { - if (backup_name_map.size() == 0) - backup_name_map = name_map; - std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; - size_t pos = child->str.rfind('.'); - if (pos == std::string::npos) - pos = child->str[0] == '\\' && prefix[0] == '\\' ? 1 : 0; - else - pos = pos + 1; - new_name = child->str.substr(0, pos) + new_name + child->str.substr(pos); - if (new_name[0] != '$' && new_name[0] != '\\') - new_name = prefix[0] + new_name; - name_map[child->str] = new_name; - if (child->type == AST_FUNCTION) - replace_result_wire_name_in_function(child, child->str, new_name); - else - child->str = new_name; - current_scope[new_name] = child; - } - if (child->type == AST_ENUM){ + + switch (child->type) { + case AST_WIRE: + case AST_MEMORY: + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_FUNCTION: + case AST_TASK: + case AST_CELL: + case AST_TYPEDEF: + case AST_ENUM_ITEM: + case AST_GENVAR: + prefix_node(child); + break; + + case AST_BLOCK: + case AST_GENBLOCK: + if (!child->str.empty()) + prefix_node(child); + break; + + case AST_ENUM: current_scope[child->str] = child; for (auto enode : child->children){ log_assert(enode->type == AST_ENUM_ITEM); - if (backup_name_map.size() == 0) - backup_name_map = name_map; - std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; - size_t pos = enode->str.rfind('.'); - if (pos == std::string::npos) - pos = enode->str[0] == '\\' && prefix[0] == '\\' ? 1 : 0; - else - pos = pos + 1; - new_name = enode->str.substr(0, pos) + new_name + enode->str.substr(pos); - if (new_name[0] != '$' && new_name[0] != '\\') - new_name = prefix[0] + new_name; - name_map[enode->str] = new_name; - - enode->str = new_name; - current_scope[new_name] = enode; + prefix_node(enode); } + break; + + default: + break; } } @@ -3781,8 +3869,14 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma // still needs to recursed-into if (type == AST_PREFIX && i == 1 && child->type == AST_IDENTIFIER) continue; - if (child->type != AST_FUNCTION && child->type != AST_TASK) - child->expand_genblock(index_var, prefix, name_map); + // functions/tasks may reference wires, constants, etc. in this scope + if (child->type == AST_FUNCTION || child->type == AST_TASK) + child->expand_genblock(index_var, prefix, name_map, false); + // continue prefixing if this child block is anonymous + else if (child->type == AST_GENBLOCK || child->type == AST_BLOCK) + child->expand_genblock(index_var, prefix, name_map, original_scope && child->str.empty()); + else + child->expand_genblock(index_var, prefix, name_map, original_scope); } @@ -4370,27 +4464,9 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) size_t argidx = 0; for (auto child : children) { - if (child->type == AST_WIRE) - { - while (child->simplify(true, false, false, 1, -1, false, true)) { } - if (!child->range_valid) - log_file_error(child->filename, child->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n", - child->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); - variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1); - variables[child->str].offset = min(child->range_left, child->range_right); - variables[child->str].is_signed = child->is_signed; - if (child->is_input && argidx < fcall->children.size()) - variables[child->str].val = fcall->children.at(argidx++)->bitsAsConst(variables[child->str].val.bits.size()); - backup_scope[child->str] = current_scope[child->str]; - current_scope[child->str] = child; - continue; - } - block->children.push_back(child->clone()); } - log_assert(variables.count(str) != 0); - while (!block->children.empty()) { AstNode *stmt = block->children.front(); @@ -4402,6 +4478,47 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) stmt->dumpAst(NULL, "stmt> "); #endif + if (stmt->type == AST_WIRE) + { + while (stmt->simplify(true, false, false, 1, -1, false, true)) { } + if (!stmt->range_valid) + log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n", + stmt->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + variables[stmt->str].val = RTLIL::Const(RTLIL::State::Sx, abs(stmt->range_left - stmt->range_right)+1); + variables[stmt->str].offset = min(stmt->range_left, stmt->range_right); + variables[stmt->str].is_signed = stmt->is_signed; + if (stmt->is_input && argidx < fcall->children.size()) { + int width = variables[stmt->str].val.bits.size(); + auto* arg_node = fcall->children.at(argidx++); + if (arg_node->type == AST_CONSTANT) { + variables[stmt->str].val = arg_node->bitsAsConst(width); + } else { + log_assert(arg_node->type == AST_REALVALUE); + variables[stmt->str].val = arg_node->realAsConst(width); + } + } + if (!backup_scope.count(stmt->str)) + backup_scope[stmt->str] = current_scope[stmt->str]; + current_scope[stmt->str] = stmt; + + block->children.erase(block->children.begin()); + continue; + } + + log_assert(variables.count(str) != 0); + + if (stmt->type == AST_LOCALPARAM) + { + while (stmt->simplify(true, false, false, 1, -1, false, true)) { } + + if (!backup_scope.count(stmt->str)) + backup_scope[stmt->str] = current_scope[stmt->str]; + current_scope[stmt->str] = stmt; + + block->children.erase(block->children.begin()); + continue; + } + if (stmt->type == AST_ASSIGN_EQ) { if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 && diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore deleted file mode 100644 index f586b33c7..000000000 --- a/frontends/ilang/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -ilang_lexer.cc -ilang_parser.output -ilang_parser.tab.cc -ilang_parser.tab.hh diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc deleted file mode 100644 index 6f1f0e8fc..000000000 --- a/frontends/ilang/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ - -GENFILES += frontends/ilang/ilang_parser.tab.cc -GENFILES += frontends/ilang/ilang_parser.tab.hh -GENFILES += frontends/ilang/ilang_parser.output -GENFILES += frontends/ilang/ilang_lexer.cc - -frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y - $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $< - -frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc - -frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l - $(Q) mkdir -p $(dir $@) - $(P) flex -o frontends/ilang/ilang_lexer.cc $< - -OBJS += frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o -OBJS += frontends/ilang/ilang_frontend.o - diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 6d72cbff5..5a40001cb 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -378,7 +378,7 @@ struct RpcFrontend : public Pass { log(" -> {\"method\": \"derive\", \"module\": \"<module-name\">, \"parameters\": {\n"); log(" \"<param-name>\": {\"type\": \"[unsigned|signed|string|real]\",\n"); log(" \"value\": \"<param-value>\"}, ...}}\n"); - log(" <- {\"frontend\": \"[ilang|verilog|...]\",\"source\": \"<source>\"}}\n"); + log(" <- {\"frontend\": \"[rtlil|verilog|...]\",\"source\": \"<source>\"}}\n"); log(" <- {\"error\": \"<error-message>\"}\n"); log(" request for the module <module-name> to be derived for a specific set of\n"); log(" parameters. <param-name> starts with \\ for named parameters, and with $\n"); diff --git a/frontends/rtlil/.gitignore b/frontends/rtlil/.gitignore new file mode 100644 index 000000000..d4a322756 --- /dev/null +++ b/frontends/rtlil/.gitignore @@ -0,0 +1,4 @@ +rtlil_lexer.cc +rtlil_parser.output +rtlil_parser.tab.cc +rtlil_parser.tab.hh diff --git a/frontends/rtlil/Makefile.inc b/frontends/rtlil/Makefile.inc new file mode 100644 index 000000000..d0c0cfcf8 --- /dev/null +++ b/frontends/rtlil/Makefile.inc @@ -0,0 +1,19 @@ + +GENFILES += frontends/rtlil/rtlil_parser.tab.cc +GENFILES += frontends/rtlil/rtlil_parser.tab.hh +GENFILES += frontends/rtlil/rtlil_parser.output +GENFILES += frontends/rtlil/rtlil_lexer.cc + +frontends/rtlil/rtlil_parser.tab.cc: frontends/rtlil/rtlil_parser.y + $(Q) mkdir -p $(dir $@) + $(P) $(BISON) -o $@ -d -r all -b frontends/rtlil/rtlil_parser $< + +frontends/rtlil/rtlil_parser.tab.hh: frontends/rtlil/rtlil_parser.tab.cc + +frontends/rtlil/rtlil_lexer.cc: frontends/rtlil/rtlil_lexer.l + $(Q) mkdir -p $(dir $@) + $(P) flex -o frontends/rtlil/rtlil_lexer.cc $< + +OBJS += frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o +OBJS += frontends/rtlil/rtlil_frontend.o + diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 973e62f2c..00c34175e 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -18,30 +18,30 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ -#include "ilang_frontend.h" +#include "rtlil_frontend.h" #include "kernel/register.h" #include "kernel/log.h" -void rtlil_frontend_ilang_yyerror(char const *s) +void rtlil_frontend_yyerror(char const *s) { - YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s); + YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_yyget_lineno(), s); } YOSYS_NAMESPACE_BEGIN -struct IlangFrontend : public Frontend { - IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } +struct RTLILFrontend : public Frontend { + RTLILFrontend() : Frontend("rtlil", "read modules from RTLIL file") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" read_ilang [filename]\n"); + log(" read_rtlil [filename]\n"); log("\n"); - log("Load modules from an ilang file to the current design. (ilang is a text\n"); + log("Load modules from an RTLIL file to the current design. (RTLIL is a text\n"); log("representation of a design in yosys's internal format.)\n"); log("\n"); log(" -nooverwrite\n"); @@ -58,27 +58,27 @@ struct IlangFrontend : public Frontend { } void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override { - ILANG_FRONTEND::flag_nooverwrite = false; - ILANG_FRONTEND::flag_overwrite = false; - ILANG_FRONTEND::flag_lib = false; + RTLIL_FRONTEND::flag_nooverwrite = false; + RTLIL_FRONTEND::flag_overwrite = false; + RTLIL_FRONTEND::flag_lib = false; - log_header(design, "Executing ILANG frontend.\n"); + log_header(design, "Executing RTLIL frontend.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-nooverwrite") { - ILANG_FRONTEND::flag_nooverwrite = true; - ILANG_FRONTEND::flag_overwrite = false; + RTLIL_FRONTEND::flag_nooverwrite = true; + RTLIL_FRONTEND::flag_overwrite = false; continue; } if (arg == "-overwrite") { - ILANG_FRONTEND::flag_nooverwrite = false; - ILANG_FRONTEND::flag_overwrite = true; + RTLIL_FRONTEND::flag_nooverwrite = false; + RTLIL_FRONTEND::flag_overwrite = true; continue; } if (arg == "-lib") { - ILANG_FRONTEND::flag_lib = true; + RTLIL_FRONTEND::flag_lib = true; continue; } break; @@ -87,12 +87,27 @@ struct IlangFrontend : public Frontend { log("Input filename: %s\n", filename.c_str()); - ILANG_FRONTEND::lexin = f; - ILANG_FRONTEND::current_design = design; - rtlil_frontend_ilang_yydebug = false; - rtlil_frontend_ilang_yyrestart(NULL); - rtlil_frontend_ilang_yyparse(); - rtlil_frontend_ilang_yylex_destroy(); + RTLIL_FRONTEND::lexin = f; + RTLIL_FRONTEND::current_design = design; + rtlil_frontend_yydebug = false; + rtlil_frontend_yyrestart(NULL); + rtlil_frontend_yyparse(); + rtlil_frontend_yylex_destroy(); + } +} RTLILFrontend; + +struct IlangFrontend : public Frontend { + IlangFrontend() : Frontend("ilang", "(deprecated) alias of read_rtlil") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log("See `help read_rtlil`.\n"); + log("\n"); + } + void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override + { + RTLILFrontend.execute(f, filename, args, design); } } IlangFrontend; diff --git a/frontends/ilang/ilang_frontend.h b/frontends/rtlil/rtlil_frontend.h index f8a152841..a420778b0 100644 --- a/frontends/ilang/ilang_frontend.h +++ b/frontends/rtlil/rtlil_frontend.h @@ -18,18 +18,18 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ -#ifndef ILANG_FRONTEND_H -#define ILANG_FRONTEND_H +#ifndef RTLIL_FRONTEND_H +#define RTLIL_FRONTEND_H #include "kernel/yosys.h" YOSYS_NAMESPACE_BEGIN -namespace ILANG_FRONTEND { +namespace RTLIL_FRONTEND { extern std::istream *lexin; extern RTLIL::Design *current_design; extern bool flag_nooverwrite; @@ -39,13 +39,13 @@ namespace ILANG_FRONTEND { YOSYS_NAMESPACE_END -extern int rtlil_frontend_ilang_yydebug; -int rtlil_frontend_ilang_yylex(void); -void rtlil_frontend_ilang_yyerror(char const *s); -void rtlil_frontend_ilang_yyrestart(FILE *f); -int rtlil_frontend_ilang_yyparse(void); -int rtlil_frontend_ilang_yylex_destroy(void); -int rtlil_frontend_ilang_yyget_lineno(void); +extern int rtlil_frontend_yydebug; +int rtlil_frontend_yylex(void); +void rtlil_frontend_yyerror(char const *s); +void rtlil_frontend_yyrestart(FILE *f); +int rtlil_frontend_yyparse(void); +int rtlil_frontend_yylex_destroy(void); +int rtlil_frontend_yyget_lineno(void); #endif diff --git a/frontends/ilang/ilang_lexer.l b/frontends/rtlil/rtlil_lexer.l index 3362ed641..295455f53 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/rtlil/rtlil_lexer.l @@ -18,7 +18,7 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ @@ -30,20 +30,20 @@ #endif #include <cstdlib> -#include "frontends/ilang/ilang_frontend.h" -#include "ilang_parser.tab.hh" +#include "frontends/rtlil/rtlil_frontend.h" +#include "rtlil_parser.tab.hh" USING_YOSYS_NAMESPACE #define YY_INPUT(buf,result,max_size) \ - result = readsome(*ILANG_FRONTEND::lexin, buf, max_size) + result = readsome(*RTLIL_FRONTEND::lexin, buf, max_size) %} %option yylineno %option noyywrap %option nounput -%option prefix="rtlil_frontend_ilang_yy" +%option prefix="rtlil_frontend_yy" %x STRING @@ -84,11 +84,11 @@ USING_YOSYS_NAMESPACE [a-z]+ { return TOK_INVALID; } -"\\"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"$"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } +"\\"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } +"$"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } +"."[0-9]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } -[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } +[0-9]+'[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; } -?[0-9]+ { char *end = nullptr; errno = 0; @@ -98,7 +98,7 @@ USING_YOSYS_NAMESPACE return TOK_INVALID; // literal out of range of long if (value < INT_MIN || value > INT_MAX) return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms) - rtlil_frontend_ilang_yylval.integer = value; + rtlil_frontend_yylval.integer = value; return TOK_INT; } @@ -131,7 +131,7 @@ USING_YOSYS_NAMESPACE yystr[j++] = yystr[i++]; } yystr[j] = 0; - rtlil_frontend_ilang_yylval.string = yystr; + rtlil_frontend_yylval.string = yystr; return TOK_STRING; } <STRING>. { yymore(); } @@ -145,6 +145,6 @@ USING_YOSYS_NAMESPACE %% // this is a hack to avoid the 'yyinput defined but not used' error msgs -void *rtlil_frontend_ilang_avoid_input_warnings() { +void *rtlil_frontend_avoid_input_warnings() { return (void*)&yyinput; } diff --git a/frontends/ilang/ilang_parser.y b/frontends/rtlil/rtlil_parser.y index 879ef4af9..646489196 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -18,15 +18,15 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ %{ #include <list> -#include "frontends/ilang/ilang_frontend.h" +#include "frontends/rtlil/rtlil_frontend.h" YOSYS_NAMESPACE_BEGIN -namespace ILANG_FRONTEND { +namespace RTLIL_FRONTEND { std::istream *lexin; RTLIL::Design *current_design; RTLIL::Module *current_module; @@ -40,12 +40,12 @@ namespace ILANG_FRONTEND { bool flag_nooverwrite, flag_overwrite, flag_lib; bool delete_current_module; } -using namespace ILANG_FRONTEND; +using namespace RTLIL_FRONTEND; YOSYS_NAMESPACE_END USING_YOSYS_NAMESPACE %} -%define api.prefix {rtlil_frontend_ilang_yy} +%define api.prefix {rtlil_frontend_yy} /* The union is defined in the header, so we need to provide all the * includes it requires @@ -53,7 +53,7 @@ USING_YOSYS_NAMESPACE %code requires { #include <string> #include <vector> -#include "frontends/ilang/ilang_frontend.h" +#include "frontends/rtlil/rtlil_frontend.h" } %union { @@ -87,7 +87,7 @@ input: attrbuf.clear(); } design { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); }; EOL: @@ -111,7 +111,7 @@ module: log("Ignoring blackbox re-definition of module %s.\n", $2); delete_current_module = true; } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of module %s.", $2).c_str()); } else if (flag_nooverwrite) { log("Ignoring re-definition of module %s.\n", $2); delete_current_module = true; @@ -129,7 +129,7 @@ module: free($2); } module_body TOK_END { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); current_module->fixup_ports(); if (delete_current_module) delete current_module; @@ -172,12 +172,12 @@ autoidx_stmt: wire_stmt: TOK_WIRE { - current_wire = current_module->addWire("$__ilang_frontend_tmp__"); + current_wire = current_module->addWire("$__rtlil_frontend_tmp__"); current_wire->attributes = attrbuf; attrbuf.clear(); } wire_options TOK_ID EOL { if (current_module->wire($4) != nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of wire %s.", $4).c_str()); current_module->rename(current_wire, $4); free($4); }; @@ -187,7 +187,7 @@ wire_options: current_wire->width = $3; } | wire_options TOK_WIDTH TOK_INVALID { - rtlil_frontend_ilang_yyerror("ilang error: invalid wire width"); + rtlil_frontend_yyerror("RTLIL error: invalid wire width"); } | wire_options TOK_UPTO { current_wire->upto = true; @@ -222,7 +222,7 @@ memory_stmt: attrbuf.clear(); } memory_options TOK_ID EOL { if (current_module->memories.count($4) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of memory %s.", $4).c_str()); current_memory->name = $4; current_module->memories[$4] = current_memory; free($4); @@ -243,7 +243,7 @@ memory_options: cell_stmt: TOK_CELL TOK_ID TOK_ID EOL { if (current_module->cell($3) != nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of cell %s.", $3).c_str()); current_cell = current_module->addCell($3, $2); current_cell->attributes = attrbuf; attrbuf.clear(); @@ -271,7 +271,7 @@ cell_body: } | cell_body TOK_CONNECT TOK_ID sigspec EOL { if (current_cell->hasPort($3)) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of cell port %s.", $3).c_str()); current_cell->setPort($3, *$4); delete $4; free($3); @@ -281,7 +281,7 @@ cell_body: proc_stmt: TOK_PROCESS TOK_ID EOL { if (current_module->processes.count($2) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str()); current_process = new RTLIL::Process; current_process->name = $2; current_process->attributes = attrbuf; @@ -342,7 +342,7 @@ case_body: assign_stmt: TOK_ASSIGN sigspec sigspec EOL { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); delete $2; delete $3; @@ -438,19 +438,19 @@ sigspec: } | TOK_ID { if (current_module->wire($1) == nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: wire %s not found", $1).c_str()); $$ = new RTLIL::SigSpec(current_module->wire($1)); free($1); } | sigspec '[' TOK_INT ']' { if ($3 >= $1->size() || $3 < 0) - rtlil_frontend_ilang_yyerror("bit index out of range"); + rtlil_frontend_yyerror("bit index out of range"); $$ = new RTLIL::SigSpec($1->extract($3)); delete $1; } | sigspec '[' TOK_INT ':' TOK_INT ']' { if ($3 >= $1->size() || $3 < 0 || $3 < $5) - rtlil_frontend_ilang_yyerror("invalid slice"); + rtlil_frontend_yyerror("invalid slice"); $$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1)); delete $1; } | @@ -477,7 +477,7 @@ sigspec_list: sigspec_list_reversed { conn_stmt: TOK_CONNECT sigspec sigspec EOL { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); current_module->connect(*$2, *$3); delete $2; delete $3; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 632dc51fd..7bbda9d49 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -54,7 +54,7 @@ USING_YOSYS_NAMESPACE # error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." #endif -#if SYMBIOTIC_VERIFIC_API_VERSION < 202006 +#if SYMBIOTIC_VERIFIC_API_VERSION < 20200801 # error "Please update your version of Symbiotic EDA flavored Verific." #endif @@ -199,12 +199,17 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k)); } else if (nl->IsFromVhdl()) { - // Expect "<binary>" + // Expect "<binary>" or plain <binary> auto p = v; if (p) { - if (*p != '"') - p = nullptr; - else { + if (*p != '"') { + auto l = strlen(p); + auto q = (char*)malloc(l+1); + strncpy(q, p, l); + q[l] = '\0'; + for(char *ptr = q; *ptr; ++ptr )*ptr = tolower(*ptr); + attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); + } else { auto *q = p+1; for (; *q != '"'; q++) if (*q != '0' && *q != '1') { @@ -213,16 +218,20 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att } if (p && *(q+1) != '\0') p = nullptr; + + if (p != nullptr) + { + auto l = strlen(p); + auto q = (char*)malloc(l+1-2); + strncpy(q, p+1, l-2); + q[l-2] = '\0'; + attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); + free(q); + } } } if (p == nullptr) - log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v); - auto l = strlen(p); - auto q = (char*)malloc(l+1-2); - strncpy(q, p+1, l-2); - q[l-2] = '\0'; - attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); - free(q); + log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v); } } } @@ -2158,6 +2167,70 @@ struct VerificPass : public Pass { log(" Dump the Verific netlist as a verilog file.\n"); log("\n"); log("\n"); + log(" verific [-work <libname>] -pp [options] <filename> [<module>]..\n"); + log("\n"); + log("Pretty print design (or just module) to the specified file from the\n"); + log("specified library. (default library when -work is not present: \"work\")\n"); + log("\n"); + log("Pretty print options:\n"); + log("\n"); + log(" -verilog\n"); + log(" Save output for Verilog/SystemVerilog design modules (default).\n"); + log("\n"); + log(" -vhdl\n"); + log(" Save output for VHDL design units.\n"); + log("\n"); + log("\n"); + log(" verific -app <application>..\n"); + log("\n"); + log("Execute SEDA formal application on loaded Verilog files.\n"); + log("\n"); + log("Application options:\n"); + log("\n"); + log(" -blacklist <filename[:lineno]>\n"); + log(" Do not run application on modules from files that match the filename\n"); + log(" or filename and line number if provided in such format.\n"); + log(" Parameter can also contain comma separated list of file locations.\n"); + log("\n"); + log(" -blfile <file>\n"); + log(" Do not run application on locations specified in file, they can represent filename\n"); + log(" or filename and location in file.\n"); + log("\n"); + log("Applications:\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + VerificFormalApplications vfa; + log("%s\n",vfa.GetHelp().c_str()); +#else + log(" WARNING: Applications only available in commercial build.\n"); + +#endif + log("\n"); + log("\n"); + log(" verific -template <name> <top_module>..\n"); + log("\n"); + log("Generate template for specified top module of loaded design.\n"); + log("\n"); + log("Template options:\n"); + log("\n"); + log(" -out\n"); + log(" Specifies output file for generated template, by default output is stdout\n"); + log("\n"); + log(" -chparam name value \n"); + log(" Generate template using this parameter value. Otherwise default parameter\n"); + log(" values will be used for templat generate functionality. This option\n"); + log(" can be specified multiple times to override multiple parameters.\n"); + log(" String values must be passed in double quotes (\").\n"); + log("\n"); + log("Templates:\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + VerificTemplateGenerator vfg; + log("%s\n",vfg.GetHelp().c_str()); +#else + log(" WARNING: Templates only available in commercial build.\n"); + log("\n"); +#endif log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"); log("https://www.symbioticeda.com/seda-suite\n"); log("\n"); @@ -2202,6 +2275,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_preserve_assignments", 1); RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); + RuntimeFlags::SetVar("veri_preserve_comments",1); + //RuntimeFlags::SetVar("vhdl_preserve_comments",1); + // Workaround for VIPER #13851 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); @@ -2399,6 +2475,161 @@ struct VerificPass : public Pass { goto check_error; } + if (argidx+1 < GetSize(args) && args[argidx] == "-app") + { + VerificFormalApplications vfa; + auto apps = vfa.GetApps(); + std::string app = args[++argidx]; + std::vector<std::string> blacklists; + if (apps.find(app) == apps.end()) + log_cmd_error("Application '%s' does not exist.\n", app.c_str()); + + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-blacklist" && argidx+1 < GetSize(args)) { + std::string line = args[++argidx]; + std::string p; + while (!(p = next_token(line, ",\t\r\n ")).empty()) + blacklists.push_back(p); + continue; + } + if (args[argidx] == "-blfile" && argidx+1 < GetSize(args)) { + std::string fn = args[++argidx]; + std::ifstream f(fn); + if (f.fail()) + log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str()); + + std::string line,p; + while (std::getline(f, line)) { + while (!(p = next_token(line, ",\t\r\n ")).empty()) + blacklists.push_back(p); + } + continue; + } + break; + } + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + MapIter mi; + VeriModule *module ; + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); + log("Running formal application '%s'.\n", app.c_str()); + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, module) { + vfa.Run(module,apps[app],blacklists); + } + goto check_error; + } + + if (argidx < GetSize(args) && args[argidx] == "-pp") + { + const char* filename = nullptr; + const char* module = nullptr; + bool mode_vhdl = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-vhdl") { + mode_vhdl = true; + continue; + } + if (args[argidx] == "-verilog") { + mode_vhdl = false; + continue; + } + + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + + if (!filename) { + filename = args[argidx].c_str(); + continue; + } + if (module) + log_cmd_error("Only one module can be specified.\n"); + module = args[argidx].c_str(); + } + + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + + if (!filename) + log_cmd_error("Filname must be specified.\n"); + + if (mode_vhdl) + vhdl_file::PrettyPrint(filename, module, work.c_str()); + else + veri_file::PrettyPrint(filename, module, work.c_str()); + goto check_error; + } + + if (argidx < GetSize(args) && args[argidx] == "-template") + { + if (!(argidx < GetSize(args))) + cmd_error(args, argidx, "No template type specified.\n"); + + VerificTemplateGenerator vfg; + auto gens = vfg.GetGenerators(); + std::string app = args[++argidx]; + if (gens.find(app) == gens.end()) + log_cmd_error("Template generator '%s' does not exist.\n", app.c_str()); + TemplateGenerator *generator = gens[app]; + if (!(argidx < GetSize(args))) + cmd_error(args, argidx, "No top module specified.\n"); + + std::string module = args[++argidx]; + VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); + VeriModule *veri_module = veri_lib ? veri_lib->GetModule(module.c_str(), 1) : nullptr; + if (!veri_module) { + log_error("Can't find module/unit '%s'.\n", module.c_str()); + } + + log("Template '%s' is running for module '%s'.\n", app.c_str(),module.c_str()); + + Map parameters(STRING_HASH); + const char *out_filename = nullptr; + + for (argidx++; argidx < GetSize(args); argidx++) { + if (generator->checkParams(args, argidx)) + continue; + if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) { + const std::string &key = args[++argidx]; + const std::string &value = args[++argidx]; + unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(), + 1 /* force_overwrite */); + if (!new_insertion) + log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str()); + continue; + } + + if (args[argidx] == "-out" && argidx+1 < GetSize(args)) { + out_filename = args[++argidx].c_str(); + continue; + } + + break; + } + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + + const char *err = generator->validate(); + if (err) + cmd_error(args, argidx, err); + + std::string val = generator->generate(veri_module, ¶meters); + + FILE *of = stdout; + if (out_filename) { + of = fopen(out_filename, "w"); + if (of == nullptr) + log_error("Can't open '%s' for writing: %s\n", out_filename, strerror(errno)); + log("Writing output to '%s'\n",out_filename); + } + fprintf(of, "%s\n",val.c_str()); + fflush(of); + if (of!=stdout) + fclose(of); + goto check_error; + } + if (GetSize(args) > argidx && args[argidx] == "-import") { std::set<Netlist*> nl_todo, nl_done; diff --git a/kernel/calc.cc b/kernel/calc.cc index ae18809d3..d54ccbc10 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -275,10 +275,15 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const return result; } -static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len) +// Shift `arg1` by `arg2` bits. +// If `direction` is +1, `arg1` is shifted right by `arg2` bits; if `direction` is -1, `arg1` is shifted left by `arg2` bits. +// If `signed2` is true, `arg2` is interpreted as a signed integer; a negative `arg2` will cause a shift in the opposite direction. +// Any required bits outside the bounds of `arg1` are padded with `vacant_bits` unless `sign_ext` is true, in which case any bits outside the left +// bounds are filled with the leftmost bit of `arg1` (arithmetic shift). +static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, bool signed2, int direction, int result_len, RTLIL::State vacant_bits = RTLIL::State::S0) { int undef_bit_pos = -1; - BigInteger offset = const2big(arg2, false, undef_bit_pos) * direction; + BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction; if (result_len < 0) result_len = arg1.bits.size(); @@ -290,9 +295,9 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co for (int i = 0; i < result_len; i++) { BigInteger pos = BigInteger(i) + offset; if (pos < 0) - result.bits[i] = RTLIL::State::S0; + result.bits[i] = vacant_bits; else if (pos >= BigInteger(int(arg1.bits.size()))) - result.bits[i] = sign_ext ? arg1.bits.back() : RTLIL::State::S0; + result.bits[i] = sign_ext ? arg1.bits.back() : vacant_bits; else result.bits[i] = arg1.bits[pos.toInt()]; } @@ -304,61 +309,36 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2 { RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, result_len, signed1); - return const_shift_worker(arg1_ext, arg2, false, -1, result_len); + return const_shift_worker(arg1_ext, arg2, false, false, -1, result_len); } RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; extend_u0(arg1_ext, max(result_len, GetSize(arg1)), signed1); - return const_shift_worker(arg1_ext, arg2, false, +1, result_len); -} - -RTLIL::Const RTLIL::const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) -{ - if (!signed1) - return const_shl(arg1, arg2, signed1, signed2, result_len); - return const_shift_worker(arg1, arg2, true, -1, result_len); + return const_shift_worker(arg1_ext, arg2, false, false, +1, result_len); } -RTLIL::Const RTLIL::const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) +RTLIL::Const RTLIL::const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { - if (!signed1) - return const_shr(arg1, arg2, signed1, signed2, result_len); - return const_shift_worker(arg1, arg2, true, +1, result_len); + return const_shift_worker(arg1, arg2, signed1, false, -1, result_len); } -static RTLIL::Const const_shift_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool, bool signed2, int result_len, RTLIL::State other_bits) +RTLIL::Const RTLIL::const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len) { - int undef_bit_pos = -1; - BigInteger offset = const2big(arg2, signed2, undef_bit_pos); - - if (result_len < 0) - result_len = arg1.bits.size(); - - RTLIL::Const result(RTLIL::State::Sx, result_len); - if (undef_bit_pos >= 0) - return result; - - for (int i = 0; i < result_len; i++) { - BigInteger pos = BigInteger(i) + offset; - if (pos < 0 || pos >= BigInteger(int(arg1.bits.size()))) - result.bits[i] = other_bits; - else - result.bits[i] = arg1.bits[pos.toInt()]; - } - - return result; + return const_shift_worker(arg1, arg2, signed1, false, +1, result_len); } RTLIL::Const RTLIL::const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) { - return const_shift_shiftx(arg1, arg2, signed1, signed2, result_len, RTLIL::State::S0); + RTLIL::Const arg1_ext = arg1; + extend_u0(arg1_ext, max(result_len, GetSize(arg1)), signed1); + return const_shift_worker(arg1_ext, arg2, false, signed2, +1, result_len); } -RTLIL::Const RTLIL::const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) +RTLIL::Const RTLIL::const_shiftx(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool, bool signed2, int result_len) { - return const_shift_shiftx(arg1, arg2, signed1, signed2, result_len, RTLIL::State::Sx); + return const_shift_worker(arg1, arg2, false, signed2, +1, result_len, RTLIL::State::Sx); } RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) diff --git a/kernel/log.cc b/kernel/log.cc index 1c1d0182e..c7ae873bc 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -19,7 +19,7 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" #if !defined(_WIN32) || defined(__MINGW32__) # include <sys/time.h> @@ -600,7 +600,7 @@ void log_dump_val_worker(RTLIL::State v) { const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) { std::stringstream buf; - ILANG_BACKEND::dump_sigspec(buf, sig, autoint); + RTLIL_BACKEND::dump_sigspec(buf, sig, autoint); if (string_buf.size() < 100) { string_buf.push_back(buf.str()); @@ -647,21 +647,21 @@ const char *log_id(RTLIL::IdString str) void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_module(buf, indent, module, module->design, false); + RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false); log("%s", buf.str().c_str()); } void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_cell(buf, indent, cell); + RTLIL_BACKEND::dump_cell(buf, indent, cell); log("%s", buf.str().c_str()); } void log_wire(RTLIL::Wire *wire, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_wire(buf, indent, wire); + RTLIL_BACKEND::dump_wire(buf, indent, wire); log("%s", buf.str().c_str()); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d7d226942..a9f585616 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -22,7 +22,7 @@ #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/verilog/preproc.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" #include <string.h> #include <algorithm> @@ -923,7 +923,7 @@ namespace { void error(int linenr) { std::stringstream buf; - ILANG_BACKEND::dump_cell(buf, " ", cell); + RTLIL_BACKEND::dump_cell(buf, " ", cell); log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", module ? module->name.c_str() : "", module ? "." : "", @@ -1035,7 +1035,11 @@ namespace { } if (cell->type.in(ID($shift), ID($shiftx))) { - param_bool(ID::A_SIGNED); + if (cell->type == ID($shiftx)) { + param_bool(ID::A_SIGNED, /*expected=*/false); + } else { + param_bool(ID::A_SIGNED); + } param_bool(ID::B_SIGNED); port(ID::A, param(ID::A_WIDTH)); port(ID::B, param(ID::B_WIDTH)); diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 73839d37a..2a54e78ec 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -522,7 +522,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) int extend_bit = ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -555,7 +555,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector<int> undef_a_shifted; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8986c8091..7a2ef4913 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -930,7 +930,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0) command = "json"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0) - command = "ilang"; + command = "rtlil"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0) command = "script"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0) @@ -1053,7 +1053,7 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".sv") == 0) command = "verilog -sv"; else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0) - command = "ilang"; + command = "rtlil"; else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".cc") == 0) command = "cxxrtl"; else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0) @@ -1065,7 +1065,7 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".json") == 0) command = "json"; else if (filename == "-") - command = "ilang"; + command = "rtlil"; else if (filename.empty()) return; else diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 83cfa5cc4..ed8b4cd49 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -39,15 +39,15 @@ the RTL Intermediate Language (RTLIL). A more detailed description of this forma is given in the next section. There is also a text representation of the RTLIL data structure that can be -parsed using the ILANG Frontend. +parsed using the RTLIL Frontend. The design data may then be transformed using a series of passes that all operate on the RTLIL representation of the design. Finally the design in RTLIL representation is converted back to text by one of the backends, namely the Verilog Backend for generating Verilog netlists -and the ILANG Backend for writing the RTLIL data in the same format that is -understood by the ILANG Frontend. +and the RTLIL Backend for writing the RTLIL data in the same format that is +understood by the RTLIL Frontend. With the exception of the AST Frontend, which is called by the high-level HDL frontends and can't be called directly by the user, all program modules are @@ -67,13 +67,13 @@ in different stages of the synthesis. \tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em] \node[process] (vlog) {Verilog Frontend}; \node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend}; - \node[process] (ilang) [right of=vhdl] {ILANG Frontend}; + \node[process] (ilang) [right of=vhdl] {RTLIL Frontend}; \node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST}; \node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend}; \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -92,8 +92,7 @@ in different stages of the synthesis. \section{The RTL Intermediate Language} -All frontends, passes and backends in Yosys operate on a design in RTLIL\footnote{The {\it Language} in {\it RTL Intermediate Language} -refers to the fact, that RTLIL also has a text representation, usually referred to as {\it Intermediate Language} (ILANG).} representation. +All frontends, passes and backends in Yosys operate on a design in RTLIL representation. The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL data. @@ -316,7 +315,7 @@ endmodule In this example there is no data path and therefore the RTLIL::Module generated by the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process. -The RTLIL::Process in ILANG syntax: +The RTLIL::Process in RTLIL syntax: \begin{lstlisting}[numbers=left,frame=single,language=rtlil] process $proc$ff_with_en_and_async_reset.v:4$1 @@ -362,7 +361,7 @@ also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object i statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine which of its cases should be active. The RTLIL::SwitchRule object then contains one RTLIL::CaseRule object per case. In this example there is a case\footnote{The -syntax {\tt 1'1} in the ILANG code specifies a constant with a length of one bit (the first ``1''), +syntax {\tt 1'1} in the RTLIL code specifies a constant with a length of one bit (the first ``1''), and this bit is a one (the second ``1'').} for {\tt \textbackslash{}reset == 1} that causes {\tt \$0\textbackslash{}q[0:0]} to be set (lines 4 and 5) and a default case that in turn contains a switch that sets {\tt \$0\textbackslash{}q[0:0]} to the value of {\tt \textbackslash{}d} if {\tt diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 555ec9175..af561d01b 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -231,7 +231,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -484,7 +484,7 @@ Commands for design navigation and investigation: \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] cd # a shortcut for 'select -module <name>' ls # list modules or objects in modules - dump # print parts of the design in ilang format + dump # print parts of the design in RTLIL format show # generate schematics using graphviz select # modify and view the list of selected objects \end{lstlisting} @@ -502,7 +502,7 @@ Commands for executing scripts or entering interactive mode: \begin{frame}[fragile]{\subsecname{} 2/3 \hspace{0pt plus 1 filll} (excerpt)} Commands for reading and elaborating the design: \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] - read_ilang # read modules from ilang file + read_rtlil # read modules from RTLIL file read_verilog # read modules from Verilog file hierarchy # check, expand and clean up design hierarchy \end{lstlisting} @@ -534,7 +534,7 @@ Commands for writing the results: write_blif # write design to BLIF file write_btor # write design to BTOR file write_edif # write design to EDIF netlist file - write_ilang # write design to ilang file + write_rtlil # write design to RTLIL file write_spice # write design to SPICE netlist file write_verilog # write design to Verilog file \end{lstlisting} diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index a9416f82a..3b61361af 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -22,7 +22,7 @@ \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -105,8 +105,7 @@ For simplicity we only discuss this version of RTLIL in this presentation. \begin{frame}{\subsecname} \begin{itemize} -\item The {\tt dump} command prints the design (or parts of it) in ILANG format. This is -a text representation of RTLIL. +\item The {\tt dump} command prints the design (or parts of it) in the text representation of RTLIL. \bigskip \item The {\tt show} command visualizes how the components in the design are connected. diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 98d42aa83..81d7a34bb 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -18,10 +18,10 @@ */ #include "kernel/yosys.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" USING_YOSYS_NAMESPACE -using namespace ILANG_BACKEND; +using namespace RTLIL_BACKEND; PRIVATE_NAMESPACE_BEGIN struct BugpointPass : public Pass { @@ -90,7 +90,7 @@ struct BugpointPass : public Pass { design->sort(); std::ofstream f("bugpoint-case.il"); - ILANG_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); + RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); f.close(); string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index cbed08a3f..a4ad861f6 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -605,7 +605,7 @@ struct ShowPass : public Pass { log(" generate a .dot file, or other <format> strings such as 'svg' or 'ps'\n"); log(" to generate files in other formats (this calls the 'dot' command).\n"); log("\n"); - log(" -lib <verilog_or_ilang_file>\n"); + log(" -lib <verilog_or_rtlil_file>\n"); log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); @@ -811,7 +811,7 @@ struct ShowPass : public Pass { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a2a428d15..90b25949d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { {".v", "verilog"}, {".sv", "verilog -sv"}, - {".il", "ilang"} + {".il", "rtlil"} }; for (auto &ext : extensions_list) diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 64fee76b3..4ae9b8895 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -4,7 +4,6 @@ OBJS += passes/opt/opt_merge.o OBJS += passes/opt/opt_mem.o OBJS += passes/opt/opt_muxtree.o OBJS += passes/opt/opt_reduce.o -OBJS += passes/opt/opt_rmdff.o OBJS += passes/opt/opt_dff.o OBJS += passes/opt/opt_share.o OBJS += passes/opt/opt_clean.o diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 77877b408..4b052d9a2 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -45,7 +45,7 @@ struct OptPass : public Pass { log(" opt_reduce [-fine] [-full]\n"); log(" opt_merge [-share_all]\n"); log(" opt_share (-full only)\n"); - log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n"); + log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n"); log(" opt_clean [-purge]\n"); log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n"); log(" while <changed design>\n"); @@ -55,9 +55,9 @@ struct OptPass : public Pass { log(" do\n"); log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n"); log(" opt_merge [-share_all]\n"); - log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n"); + log(" opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] (except when called with -noff)\n"); log(" opt_clean [-purge]\n"); - log(" while <changed design in opt_rmdff>\n"); + log(" while <changed design in opt_dff>\n"); log("\n"); log("Note: Options in square brackets (such as [-keepdc]) are passed through to\n"); log("the opt_* commands when given to 'opt'.\n"); @@ -70,7 +70,7 @@ struct OptPass : public Pass { std::string opt_expr_args; std::string opt_reduce_args; std::string opt_merge_args; - std::string opt_rmdff_args; + std::string opt_dff_args; bool opt_share = false; bool fast_mode = false; bool noff_mode = false; @@ -113,11 +113,19 @@ struct OptPass : public Pass { } if (args[argidx] == "-keepdc") { opt_expr_args += " -keepdc"; - opt_rmdff_args += " -keepdc"; + opt_dff_args += " -keepdc"; + continue; + } + if (args[argidx] == "-nodffe") { + opt_dff_args += " -nodffe"; + continue; + } + if (args[argidx] == "-nosdff") { + opt_dff_args += " -nosdff"; continue; } if (args[argidx] == "-sat") { - opt_rmdff_args += " -sat"; + opt_dff_args += " -sat"; continue; } if (args[argidx] == "-share_all") { @@ -143,7 +151,7 @@ struct OptPass : public Pass { Pass::call(design, "opt_merge" + opt_merge_args); design->scratchpad_unset("opt.did_something"); if (!noff_mode) - Pass::call(design, "opt_rmdff" + opt_rmdff_args); + Pass::call(design, "opt_dff" + opt_dff_args); if (design->scratchpad_get_bool("opt.did_something") == false) break; Pass::call(design, "opt_clean" + opt_clean_args); @@ -163,7 +171,7 @@ struct OptPass : public Pass { if (opt_share) Pass::call(design, "opt_share"); if (!noff_mode) - Pass::call(design, "opt_rmdff" + opt_rmdff_args); + Pass::call(design, "opt_dff" + opt_dff_args); Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_expr" + opt_expr_args); if (design->scratchpad_get_bool("opt.did_something") == false) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 44de60b48..5370881d3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -55,7 +55,12 @@ struct keep_cache_t if (!module->get_bool_attribute(ID::keep)) { bool found_keep = false; for (auto cell : module->cells()) - if (query(cell, true /* ignore_specify */)) { + if (query(cell, true /* ignore_specify_mem */)) { + found_keep = true; + break; + } + for (auto wire : module->wires()) + if (wire->get_bool_attribute(ID::keep)) { found_keep = true; break; } @@ -65,12 +70,12 @@ struct keep_cache_t return cache[module]; } - bool query(Cell *cell, bool ignore_specify = false) + bool query(Cell *cell, bool ignore_specify_mem = false) { - if (cell->type.in(ID($memwr), ID($meminit), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) + if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) return true; - if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule))) + if (!ignore_specify_mem && cell->type.in(ID($memwr), ID($meminit), ID($specify2), ID($specify3), ID($specrule))) return true; if (cell->has_keep_attr()) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc deleted file mode 100644 index 8f7628a4a..000000000 --- a/passes/opt/opt_rmdff.cc +++ /dev/null @@ -1,711 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/log.h" -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/satgen.h" -#include "kernel/sigtools.h" -#include <stdio.h> -#include <stdlib.h> - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -SigMap assign_map, dff_init_map; -SigSet<RTLIL::Cell*> mux_drivers; -dict<SigBit, RTLIL::Cell*> bit2driver; -dict<SigBit, pool<SigBit>> init_attributes; - -bool keepdc; -bool sat; - -void remove_init_attr(SigSpec sig) -{ - for (auto bit : assign_map(sig)) - if (init_attributes.count(bit)) - for (auto wbit : init_attributes.at(bit)) - wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx; -} - -bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) -{ - SigSpec sig_set, sig_clr; - State pol_set, pol_clr; - - if (cell->hasPort(ID::S)) - sig_set = cell->getPort(ID::S); - - if (cell->hasPort(ID::R)) - sig_clr = cell->getPort(ID::R); - - if (cell->hasPort(ID::SET)) - sig_set = cell->getPort(ID::SET); - - if (cell->hasPort(ID::CLR)) - sig_clr = cell->getPort(ID::CLR); - - log_assert(GetSize(sig_set) == GetSize(sig_clr)); - - if (cell->type.begins_with("$_DFFSR_")) { - pol_set = cell->type[9] == 'P' ? State::S1 : State::S0; - pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0; - } else - if (cell->type.begins_with("$_DLATCHSR_")) { - pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; - pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; - } else - if (cell->type.in(ID($dffsr), ID($dlatchsr))) { - pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0; - pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0; - } else - log_abort(); - - State npol_set = pol_set == State::S0 ? State::S1 : State::S0; - State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0; - - SigSpec sig_d = cell->getPort(ID::D); - SigSpec sig_q = cell->getPort(ID::Q); - - bool did_something = false; - bool proper_sr = false; - bool used_pol_set = false; - bool used_pol_clr = false; - bool hasreset = false; - Const reset_val; - SigSpec sig_reset; - - for (int i = 0; i < GetSize(sig_set); i++) - { - SigBit s = sig_set[i], c = sig_clr[i]; - - if (s != npol_set || c != npol_clr) - hasreset = true; - - if (s == pol_set || c == pol_clr) - { - log("Constantly %s Q bit %s for SR cell %s (%s) from module %s.\n", - s == pol_set ? "set" : "cleared", log_signal(sig_q[i]), - log_id(cell), log_id(cell->type), log_id(mod)); - - remove_init_attr(sig_q[i]); - mod->connect(sig_q[i], s == pol_set ? State::S1 : State::S0); - sig_set.remove(i); - sig_clr.remove(i); - sig_d.remove(i); - sig_q.remove(i--); - did_something = true; - continue; - } - if (sig_reset.empty() && s.wire != nullptr) sig_reset = s; - if (sig_reset.empty() && c.wire != nullptr) sig_reset = c; - - if (s.wire != nullptr && s != sig_reset) proper_sr = true; - if (c.wire != nullptr && c != sig_reset) proper_sr = true; - - if ((s.wire == nullptr) != (c.wire == nullptr)) { - if (s.wire != nullptr) used_pol_set = true; - if (c.wire != nullptr) used_pol_clr = true; - reset_val.bits.push_back(c.wire == nullptr ? State::S1 : State::S0); - } else - proper_sr = true; - } - - if (!hasreset) - proper_sr = false; - - if (GetSize(sig_set) == 0) - { - log("Removing %s (%s) from module %s.\n", log_id(cell), log_id(cell->type), log_id(mod)); - mod->remove(cell); - return true; - } - - if (cell->type.in(ID($dffsr), ID($dlatchsr))) - { - cell->setParam(ID::WIDTH, GetSize(sig_d)); - cell->setPort(ID::SET, sig_set); - cell->setPort(ID::CLR, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - } - else - { - cell->setPort(ID::S, sig_set); - cell->setPort(ID::R, sig_clr); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - } - - if (proper_sr) - return did_something; - - if (used_pol_set && used_pol_clr && pol_set != pol_clr) - return did_something; - - if (cell->type == ID($dlatchsr)) - return did_something; - - State unified_pol = used_pol_set ? pol_set : pol_clr; - - if (cell->type == ID($dffsr)) - { - if (hasreset) - { - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod)); - - cell->type = ID($adff); - cell->setParam(ID::ARST_POLARITY, unified_pol); - cell->setParam(ID::ARST_VALUE, reset_val); - cell->setPort(ID::ARST, sig_reset); - - cell->unsetParam(ID::SET_POLARITY); - cell->unsetParam(ID::CLR_POLARITY); - cell->unsetPort(ID::SET); - cell->unsetPort(ID::CLR); - } - else - { - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod)); - - cell->type = ID($dff); - cell->unsetParam(ID::SET_POLARITY); - cell->unsetParam(ID::CLR_POLARITY); - cell->unsetPort(ID::SET); - cell->unsetPort(ID::CLR); - } - - return true; - } - - if (!hasreset) - { - IdString new_type; - - if (cell->type.begins_with("$_DFFSR_")) - new_type = stringf("$_DFF_%c_", cell->type[8]); - else if (cell->type.begins_with("$_DLATCHSR_")) - new_type = stringf("$_DLATCH_%c_", cell->type[11]); - else - log_abort(); - - log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod)); - - cell->type = new_type; - cell->unsetPort(ID::S); - cell->unsetPort(ID::R); - - return true; - } - - return did_something; -} - -bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) -{ - SigSpec sig_e; - State on_state, off_state; - - if (dlatch->type == ID($dlatch)) { - sig_e = assign_map(dlatch->getPort(ID::EN)); - on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0; - off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1; - } else - if (dlatch->type == ID($_DLATCH_P_)) { - sig_e = assign_map(dlatch->getPort(ID::E)); - on_state = State::S1; - off_state = State::S0; - } else - if (dlatch->type == ID($_DLATCH_N_)) { - sig_e = assign_map(dlatch->getPort(ID::E)); - on_state = State::S0; - off_state = State::S1; - } else - log_abort(); - - if (sig_e == off_state) - { - RTLIL::Const val_init; - for (auto bit : dff_init_map(dlatch->getPort(ID::Q))) - val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx); - mod->connect(dlatch->getPort(ID::Q), val_init); - goto delete_dlatch; - } - - if (sig_e == on_state) - { - mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D)); - goto delete_dlatch; - } - - return false; - -delete_dlatch: - log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod)); - remove_init_attr(dlatch->getPort(ID::Q)); - mod->remove(dlatch); - return true; -} - -bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) -{ - RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e; - RTLIL::Const val_cp, val_rp, val_rv, val_ep; - - if (dff->type == ID($_FF_)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - } - else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1); - } - else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 && - (dff->type[6] == 'N' || dff->type[6] == 'P') && - (dff->type[7] == 'N' || dff->type[7] == 'P') && - (dff->type[8] == '0' || dff->type[8] == '1')) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - sig_r = dff->getPort(ID::R); - val_cp = RTLIL::Const(dff->type[6] == 'P', 1); - val_rp = RTLIL::Const(dff->type[7] == 'P', 1); - val_rv = RTLIL::Const(dff->type[8] == '1', 1); - } - else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 && - (dff->type[7] == 'N' || dff->type[7] == 'P') && - (dff->type[8] == 'N' || dff->type[8] == 'P')) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::C); - sig_e = dff->getPort(ID::E); - val_cp = RTLIL::Const(dff->type[7] == 'P', 1); - val_ep = RTLIL::Const(dff->type[8] == 'P', 1); - } - else if (dff->type == ID($ff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - } - else if (dff->type == ID($dff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - } - else if (dff->type == ID($dffe)) { - sig_e = dff->getPort(ID::EN); - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1); - } - else if (dff->type == ID($adff)) { - sig_d = dff->getPort(ID::D); - sig_q = dff->getPort(ID::Q); - sig_c = dff->getPort(ID::CLK); - sig_r = dff->getPort(ID::ARST); - val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1); - val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1); - val_rv = dff->parameters[ID::ARST_VALUE]; - } - else - log_abort(); - - assign_map.apply(sig_d); - assign_map.apply(sig_q); - assign_map.apply(sig_c); - assign_map.apply(sig_r); - - bool has_init = false; - RTLIL::Const val_init; - for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) { - if (bit.wire == NULL || keepdc) - has_init = true; - val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx); - } - - if (dff->type.in(ID($ff), ID($dff)) && mux_drivers.has(sig_d)) { - std::set<RTLIL::Cell*> muxes; - mux_drivers.find(sig_d, muxes); - for (auto mux : muxes) { - RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID::A)); - RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID::B)); - if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) { - mod->connect(sig_q, sig_b); - goto delete_dff; - } - if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) { - mod->connect(sig_q, sig_a); - goto delete_dff; - } - } - } - - // If clock is driven by a constant and (i) no reset signal - // (ii) Q has no initial value - // (iii) initial value is same as reset value - if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) { - if (val_rv.bits.size() == 0) - val_rv = val_init; - // Q is permanently reset value or initial value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - // If D is fully undefined and reset signal present and (i) Q has no initial value - // (ii) initial value is same as reset value - if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) { - // Q is permanently reset value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - // If D is fully undefined and no reset signal and Q has an initial value - if (sig_d.is_fully_undef() && !sig_r.size() && has_init) { - // Q is permanently initial value - mod->connect(sig_q, val_init); - goto delete_dff; - } - - // If D is fully constant and (i) no reset signal - // (ii) reset value is same as constant D - // and (a) has no initial value - // (b) initial value same as constant D - if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) { - // Q is permanently D - mod->connect(sig_q, sig_d); - goto delete_dff; - } - - // If D input is same as Q output and (i) no reset signal - // (ii) no initial signal - // (iii) initial value is same as reset value - if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) { - // Q is permanently reset value or initial value - if (sig_r.size()) - mod->connect(sig_q, val_rv); - else if (has_init) - mod->connect(sig_q, val_init); - goto delete_dff; - } - - // If reset signal is present, and is fully constant - if (!sig_r.empty() && sig_r.is_fully_const()) - { - // If reset value is permanently active or if reset is undefined - if (sig_r == val_rp || sig_r.is_fully_undef()) { - // Q is permanently reset value - mod->connect(sig_q, val_rv); - goto delete_dff; - } - - log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - - if (dff->type == ID($adff)) { - dff->type = ID($dff); - dff->unsetPort(ID::ARST); - dff->unsetParam(ID::ARST_POLARITY); - dff->unsetParam(ID::ARST_VALUE); - return true; - } - - log_assert(dff->type.begins_with("$_DFF_")); - dff->type = stringf("$_DFF_%c_", + dff->type[6]); - dff->unsetPort(ID::R); - } - - // If enable signal is present, and is fully constant - if (!sig_e.empty() && sig_e.is_fully_const()) - { - // If enable value is permanently inactive - if (sig_e != val_ep) { - // Q is permanently initial value - mod->connect(sig_q, val_init); - goto delete_dff; - } - - log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - - if (dff->type == ID($dffe)) { - dff->type = ID($dff); - dff->unsetPort(ID::EN); - dff->unsetParam(ID::EN_POLARITY); - return true; - } - - log_assert(dff->type.begins_with("$_DFFE_")); - dff->type = stringf("$_DFF_%c_", + dff->type[7]); - dff->unsetPort(ID::E); - } - - if (sat && has_init && (!sig_r.size() || val_init == val_rv)) - { - bool removed_sigbits = false; - - ezSatPtr ez; - SatGen satgen(ez.get(), &assign_map); - pool<Cell*> sat_cells; - - std::function<void(Cell*)> sat_import_cell = [&](Cell *c) { - if (!sat_cells.insert(c).second) - return; - if (!satgen.importCell(c)) - return; - for (auto &conn : c->connections()) { - if (!c->input(conn.first)) - continue; - for (auto bit : assign_map(conn.second)) - if (bit2driver.count(bit)) - sat_import_cell(bit2driver.at(bit)); - } - }; - - // For each register bit, try to prove that it cannot change from the initial value. If so, remove it - for (int position = 0; position < GetSize(sig_d); position += 1) { - RTLIL::SigBit q_sigbit = sig_q[position]; - RTLIL::SigBit d_sigbit = sig_d[position]; - - if ((!q_sigbit.wire) || (!d_sigbit.wire)) - continue; - - if (!bit2driver.count(d_sigbit)) - continue; - - sat_import_cell(bit2driver.at(d_sigbit)); - - RTLIL::State sigbit_init_val = val_init[position]; - if (sigbit_init_val != State::S0 && sigbit_init_val != State::S1) - continue; - - int init_sat_pi = satgen.importSigSpec(sigbit_init_val).front(); - int q_sat_pi = satgen.importSigBit(q_sigbit); - int d_sat_pi = satgen.importSigBit(d_sigbit); - - // Try to find out whether the register bit can change under some circumstances - bool counter_example_found = ez->solve(ez->IFF(q_sat_pi, init_sat_pi), ez->NOT(ez->IFF(d_sat_pi, init_sat_pi))); - - // If the register bit cannot change, we can replace it with a constant - if (!counter_example_found) - { - log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0, - position, log_id(dff), log_id(dff->type), log_id(mod)); - - SigSpec tmp = dff->getPort(ID::D); - tmp[position] = sigbit_init_val; - dff->setPort(ID::D, tmp); - - removed_sigbits = true; - } - } - - if (removed_sigbits) { - handle_dff(mod, dff); - return true; - } - } - - - return false; - -delete_dff: - log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); - remove_init_attr(dff->getPort(ID::Q)); - mod->remove(dff); - - for (auto &entry : bit2driver) - if (entry.second == dff) - bit2driver.erase(entry.first); - - return true; -} - -struct OptRmdffPass : public Pass { - OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" opt_rmdff [-keepdc] [-sat] [selection]\n"); - log("\n"); - log("This pass identifies flip-flops with constant inputs and replaces them with\n"); - log("a constant driver.\n"); - log("\n"); - log(" -sat\n"); - log(" additionally invoke SAT solver to detect and remove flip-flops (with \n"); - log(" non-constant inputs) that can also be replaced with a constant driver\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - int total_count = 0, total_initdrv = 0; - log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n"); - - keepdc = false; - sat = false; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-keepdc") { - keepdc = true; - continue; - } - if (args[argidx] == "-sat") { - sat = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - for (auto module : design->selected_modules()) { - pool<SigBit> driven_bits; - dict<SigBit, State> init_bits; - - assign_map.set(module); - dff_init_map.set(module); - mux_drivers.clear(); - bit2driver.clear(); - init_attributes.clear(); - - for (auto wire : module->wires()) - { - if (wire->attributes.count(ID::init) != 0) { - Const initval = wire->attributes.at(ID::init); - for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) - if (initval[i] == State::S0 || initval[i] == State::S1) - dff_init_map.add(SigBit(wire, i), initval[i]); - for (int i = 0; i < GetSize(wire); i++) { - SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit); - if (mapped_bit.wire) { - init_attributes[mapped_bit].insert(wire_bit); - if (i < GetSize(initval)) - init_bits[mapped_bit] = initval[i]; - } - } - } - - if (wire->port_input) { - for (auto bit : assign_map(wire)) - driven_bits.insert(bit); - } - } - - std::vector<RTLIL::IdString> dff_list; - std::vector<RTLIL::IdString> dffsr_list; - std::vector<RTLIL::IdString> dlatch_list; - for (auto cell : module->cells()) - { - for (auto &conn : cell->connections()) { - bool is_output = cell->output(conn.first); - if (is_output || !cell->known()) - for (auto bit : assign_map(conn.second)) { - if (is_output) - bit2driver[bit] = cell; - driven_bits.insert(bit); - } - } - - if (cell->type.in(ID($mux), ID($pmux))) { - if (cell->getPort(ID::A).size() == cell->getPort(ID::B).size()) - mux_drivers.insert(assign_map(cell->getPort(ID::Y)), cell); - continue; - } - - if (!design->selected(module, cell)) - continue; - - if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_), - ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_), ID($dffsr), - ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_), - ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_), ID($dlatchsr))) - dffsr_list.push_back(cell->name); - - if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), - ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), - ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_), - ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), - ID($ff), ID($dff), ID($dffe), ID($adff))) - dff_list.push_back(cell->name); - - if (cell->type.in(ID($dlatch), ID($_DLATCH_P_), ID($_DLATCH_N_))) - dlatch_list.push_back(cell->name); - } - - for (auto &id : dffsr_list) { - if (module->cell(id) != nullptr && - handle_dffsr(module, module->cells_[id])) - total_count++; - } - - for (auto &id : dff_list) { - if (module->cell(id) != nullptr && - handle_dff(module, module->cells_[id])) - total_count++; - } - - for (auto &id : dlatch_list) { - if (module->cell(id) != nullptr && - handle_dlatch(module, module->cells_[id])) - total_count++; - } - - SigSpec const_init_sigs; - - for (auto bit : init_bits) - if (!driven_bits.count(bit.first)) - const_init_sigs.append(bit.first); - - const_init_sigs.sort_and_unify(); - - for (SigSpec sig : const_init_sigs.chunks()) - { - Const val; - - for (auto bit : sig) - val.bits.push_back(init_bits.at(bit)); - - log("Promoting init spec %s = %s to constant driver in module %s.\n", - log_signal(sig), log_signal(val), log_id(module)); - - module->connect(sig, val); - remove_init_attr(sig); - total_initdrv++; - } - } - - assign_map.clear(); - mux_drivers.clear(); - bit2driver.clear(); - init_attributes.clear(); - - if (total_count || total_initdrv) - design->scratchpad_set_bool("opt.did_something", true); - - if (total_initdrv) - log("Promoted %d init specs to constant drivers.\n", total_initdrv); - - if (total_count) - log("Replaced %d DFF cells.\n", total_count); - } -} OptRmdffPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index db21cef28..53296699c 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -30,8 +30,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -SigMap assign_map; - struct OpMuxConn { RTLIL::SigSpec sig; RTLIL::Cell *mux; @@ -157,9 +155,9 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name) return false; } -ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sigmap) +ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap) { - auto sig = (*sigmap)(cell->getPort(port_name)); + auto sig = sigmap(cell->getPort(port_name)); RTLIL::SigSpec sign = decode_port_sign(cell, port_name); RTLIL::IdString semantics = decode_port_semantics(cell, port_name); @@ -169,7 +167,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sig return ExtSigSpec(sig, sign, is_signed, semantics); } -void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand) +void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap) { std::vector<ExtSigSpec> muxed_operands; int max_width = 0; @@ -177,10 +175,10 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto op = p.op; RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, &assign_map) == operand) + if (decode_port(op, ID::A, sigmap) == operand) muxed_port_name = ID::B; - auto operand = decode_port(op, muxed_port_name, &assign_map); + auto operand = decode_port(op, muxed_port_name, sigmap); if (operand.sig.size() > max_width) max_width = operand.sig.size(); @@ -190,11 +188,13 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< auto shared_op = ports[0].op; if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; })) - max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int()); - + max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int()); - for (auto &operand : muxed_operands) + for (auto &operand : muxed_operands) { operand.sig.extend_u0(max_width, operand.is_signed); + if (operand.sign != muxed_operands[0].sign) + operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed)); + } for (const auto& p : ports) { auto op = p.op; @@ -203,61 +203,58 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< module->remove(op); } - for (auto &muxed_op : muxed_operands) - if (muxed_op.sign != muxed_operands[0].sign) - muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed)); - - RTLIL::SigSpec mux_y = mux->getPort(ID::Y); RTLIL::SigSpec mux_a = mux->getPort(ID::A); RTLIL::SigSpec mux_b = mux->getPort(ID::B); RTLIL::SigSpec mux_s = mux->getPort(ID::S); + int conn_width = ports[0].sig.size(); + int conn_mux_offset = ports[0].mux_port_offset; + int conn_op_offset = ports[0].op_outsig_offset; + RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width); RTLIL::SigSpec shared_pmux_b; RTLIL::SigSpec shared_pmux_s; - int conn_width = ports[0].sig.size(); - int conn_offset = ports[0].mux_port_offset; - - shared_op->setPort(ID::Y, shared_op->getPort(ID::Y).extract(0, conn_width)); + // Make a new wire to avoid false equivalence with whatever the former shared output was connected to. + Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width); + SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width); - if (mux->type == ID($pmux)) { - shared_pmux_s = RTLIL::SigSpec(); - - for (const auto &p : ports) { + for (int i = 0; i < GetSize(ports); i++) { + auto &p = ports[i]; + auto &op = muxed_operands[i]; + if (p.mux_port_id == GetSize(mux_s)) { + shared_pmux_a = op.sig; + mux_a.replace(conn_mux_offset, new_sig_out); + } else { shared_pmux_s.append(mux_s[p.mux_port_id]); - mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID::Y)); + shared_pmux_b.append(op.sig); + mux_b.replace(p.mux_port_id * mux_a.size() + conn_mux_offset, new_sig_out); } - } else { - shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)}; - mux_a.replace(conn_offset, shared_op->getPort(ID::Y)); - mux_b.replace(conn_offset, shared_op->getPort(ID::Y)); } mux->setPort(ID::A, mux_a); mux->setPort(ID::B, mux_b); - mux->setPort(ID::Y, mux_y); mux->setPort(ID::S, mux_s); - for (const auto &op : muxed_operands) - shared_pmux_b.append(op.sig); - - auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + SigSpec mux_to_oper; + if (GetSize(shared_pmux_s) == 1) { + mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + } else { + mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + } if (shared_op->type.in(ID($alu))) { - RTLIL::SigSpec alu_x = shared_op->getPort(ID::X); - RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO); - - shared_op->setPort(ID::X, alu_x.extract(0, conn_width)); - shared_op->setPort(ID::CO, alu_co.extract(0, conn_width)); + shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out))); + shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); + shared_op->setPort(ID::Y, new_out); if (!is_fine) - shared_op->setParam(ID::Y_WIDTH, conn_width); + shared_op->setParam(ID::Y_WIDTH, GetSize(new_out)); - if (decode_port(shared_op, ID::A, &assign_map) == operand) { + if (decode_port(shared_op, ID::A, sigmap) == operand) { shared_op->setPort(ID::B, mux_to_oper); if (!is_fine) shared_op->setParam(ID::B_WIDTH, max_width); @@ -275,17 +272,7 @@ typedef struct { } merged_op_t; -template <typename T> void remove_val(std::vector<T> &v, const std::vector<T> &vals) -{ - auto val_iter = vals.rbegin(); - for (auto i = v.rbegin(); i != v.rend(); ++i) - if ((val_iter != vals.rend()) && (*i == *val_iter)) { - v.erase(i.base() - 1); - ++val_iter; - } -} - -void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand) +void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand, const SigMap &sigmap) { auto it = ports.begin(); ExtSigSpec seed; @@ -295,11 +282,11 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe auto op = p->op; RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, &assign_map) == shared_operand) { + if (decode_port(op, ID::A, sigmap) == shared_operand) { muxed_port_name = ID::B; } - auto operand = decode_port(op, muxed_port_name, &assign_map); + auto operand = decode_port(op, muxed_port_name, sigmap); if (seed.empty()) seed = operand; @@ -312,7 +299,7 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe } } -ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users) +ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users, const SigMap &sigmap) { std::set<RTLIL::Cell *> ops_using_operand; std::set<RTLIL::Cell *> ops_set; @@ -324,7 +311,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon auto op_a = seed->op; for (RTLIL::IdString port_name : {ID::A, ID::B}) { - oper = decode_port(op_a, port_name, &assign_map); + oper = decode_port(op_a, port_name, sigmap); auto operand_users = operand_to_users.at(oper); if (operand_users.size() == 1) @@ -345,132 +332,6 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon return ExtSigSpec(); } -dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL::SigSpec> &op_outbit_to_outsig, - dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator, - dict<RTLIL::SigBit, RTLIL::SigSpec> &op_aux_to_outsig) -{ - dict<RTLIL::SigSpec, int> op_outsig_user_track; - dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map; - - std::function<void(RTLIL::SigSpec)> remove_outsig = [&](RTLIL::SigSpec outsig) { - for (auto op_outbit : outsig) - op_outbit_to_outsig.erase(op_outbit); - - if (op_mux_conn_map.count(outsig)) - op_mux_conn_map.erase(outsig); - }; - - std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) { - auto aux_outsig = op_aux_to_outsig.at(auxbit); - auto op = outsig_to_operator.at(aux_outsig); - auto op_outsig = assign_map(op->getPort(ID::Y)); - remove_outsig(op_outsig); - - for (auto aux_outbit : aux_outsig) - op_aux_to_outsig.erase(aux_outbit); - }; - - std::function<void(RTLIL::Cell *)> find_op_mux_conns = [&](RTLIL::Cell *mux) { - RTLIL::SigSpec sig; - int mux_port_size; - - if (mux->type.in(ID($mux), ID($_MUX_))) { - mux_port_size = mux->getPort(ID::A).size(); - sig = RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)}; - } else { - mux_port_size = mux->getPort(ID::A).size(); - sig = mux->getPort(ID::B); - } - - auto mux_insig = assign_map(sig); - - for (int i = 0; i < mux_insig.size(); ++i) { - if (op_aux_to_outsig.count(mux_insig[i])) { - remove_outsig_from_aux_bit(mux_insig[i]); - continue; - } - - if (!op_outbit_to_outsig.count(mux_insig[i])) - continue; - - auto op_outsig = op_outbit_to_outsig.at(mux_insig[i]); - - if (op_mux_conn_map.count(op_outsig)) { - remove_outsig(op_outsig); - continue; - } - - int mux_port_id = i / mux_port_size; - int mux_port_offset = i % mux_port_size; - - int op_outsig_offset; - for (op_outsig_offset = 0; op_outsig[op_outsig_offset] != mux_insig[i]; ++op_outsig_offset) - ; - - int j = op_outsig_offset; - do { - if (!op_outbit_to_outsig.count(mux_insig[i])) - break; - - if (op_outbit_to_outsig.at(mux_insig[i]) != op_outsig) - break; - - ++i; - ++j; - } while ((i / mux_port_size == mux_port_id) && (j < op_outsig.size())); - - int op_conn_width = j - op_outsig_offset; - OpMuxConn inp = { - op_outsig.extract(op_outsig_offset, op_conn_width), - mux, - outsig_to_operator.at(op_outsig), - mux_port_id, - mux_port_offset, - op_outsig_offset, - }; - - op_mux_conn_map[op_outsig] = inp; - - --i; - } - }; - - std::function<void(RTLIL::SigSpec)> remove_connected_ops = [&](RTLIL::SigSpec sig) { - auto mux_insig = assign_map(sig); - for (auto outbit : mux_insig) { - if (op_aux_to_outsig.count(outbit)) { - remove_outsig_from_aux_bit(outbit); - continue; - } - - if (!op_outbit_to_outsig.count(outbit)) - continue; - - remove_outsig(op_outbit_to_outsig.at(outbit)); - } - }; - - for (auto cell : module->cells()) { - if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) { - remove_connected_ops(cell->getPort(ID::S)); - find_op_mux_conns(cell); - } else { - for (auto &conn : cell->connections()) - if (cell->input(conn.first)) - remove_connected_ops(conn.second); - } - } - - for (auto w : module->wires()) { - if (!w->port_output) - continue; - - remove_connected_ops(w); - } - - return op_mux_conn_map; -} - struct OptSharePass : public Pass { OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {} void help() override @@ -495,37 +356,46 @@ struct OptSharePass : public Pass { extra_args(args, 1, design); for (auto module : design->selected_modules()) { - assign_map.clear(); - assign_map.set(module); + SigMap sigmap(module); + + dict<RTLIL::SigBit, int> bit_users; + + for (auto cell : module->cells()) + for (auto conn : cell->connections()) + for (auto bit : conn.second) + bit_users[sigmap(bit)]++; + + for (auto wire : module->wires()) + if (wire->port_id != 0) + for (auto bit : SigSpec(wire)) + bit_users[sigmap(bit)]++; std::map<ExtSigSpec, std::set<RTLIL::Cell *>> operand_to_users; - dict<RTLIL::SigSpec, RTLIL::Cell *> outsig_to_operator; - dict<RTLIL::SigBit, RTLIL::SigSpec> op_outbit_to_outsig; - dict<RTLIL::SigBit, RTLIL::SigSpec> op_aux_to_outsig; + dict<RTLIL::SigBit, std::pair<RTLIL::Cell *, int>> op_outbit_to_outsig; bool any_shared_operands = false; - std::vector<ExtSigSpec> op_insigs; - for (auto cell : module->cells()) { + for (auto cell : module->selected_cells()) { if (!cell_supported(cell)) continue; + bool skip = false; if (cell->type == ID($alu)) { for (RTLIL::IdString port_name : {ID::X, ID::CO}) { - auto mux_insig = assign_map(cell->getPort(port_name)); - outsig_to_operator[mux_insig] = cell; - for (auto outbit : mux_insig) - op_aux_to_outsig[outbit] = mux_insig; + for (auto outbit : sigmap(cell->getPort(port_name))) + if (bit_users[outbit] > 1) + skip = true; } } - auto mux_insig = assign_map(cell->getPort(ID::Y)); - outsig_to_operator[mux_insig] = cell; - for (auto outbit : mux_insig) - op_outbit_to_outsig[outbit] = mux_insig; + if (skip) + continue; + + auto mux_insig = sigmap(cell->getPort(ID::Y)); + for (int i = 0; i < GetSize(mux_insig); i++) + op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i); for (RTLIL::IdString port_name : {ID::A, ID::B}) { - auto op_insig = decode_port(cell, port_name, &assign_map); - op_insigs.push_back(op_insig); + auto op_insig = decode_port(cell, port_name, sigmap); operand_to_users[op_insig].insert(cell); if (operand_to_users[op_insig].size() > 1) any_shared_operands = true; @@ -537,34 +407,79 @@ struct OptSharePass : public Pass { // Operator outputs need to be exclusively connected to the $mux inputs in order to be mergeable. Hence we count to // how many points are operator output bits connected. - dict<RTLIL::SigSpec, OpMuxConn> op_mux_conn_map = - find_valid_op_mux_conns(module, op_outbit_to_outsig, outsig_to_operator, op_aux_to_outsig); + std::vector<merged_op_t> merged_ops; - // Group op connections connected to same ports of the same $mux. Sort them in ascending order of their port offset - dict<RTLIL::Cell*, std::vector<std::set<OpMuxConn>>> mux_port_op_conns; - for (auto& val: op_mux_conn_map) { - OpMuxConn p = val.second; - auto& mux_port_conns = mux_port_op_conns[p.mux]; + for (auto mux : module->selected_cells()) { + if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux))) + continue; - if (mux_port_conns.size() == 0) { - int mux_port_num; + int mux_port_size = GetSize(mux->getPort(ID::A)); + int mux_port_num = GetSize(mux->getPort(ID::S)) + 1; - if (p.mux->type.in(ID($mux), ID($_MUX_))) - mux_port_num = 2; - else - mux_port_num = p.mux->getPort(ID::S).size(); + RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)}); + std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num); + int found = 0; - mux_port_conns.resize(mux_port_num); - } + for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) { + SigSpec mux_insig; + if (mux_port_id == mux_port_num - 1) { + mux_insig = sigmap(mux->getPort(ID::A)); + } else { + mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size)); + } - mux_port_conns[p.mux_port_id].insert(p); - } + for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) { + if (!op_outbit_to_outsig.count(mux_insig[mux_port_offset])) + continue; - std::vector<merged_op_t> merged_ops; - for (auto& val: mux_port_op_conns) { + RTLIL::Cell *cell; + int op_outsig_offset; + std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]); + SigSpec op_outsig = sigmap(cell->getPort(ID::Y)); + int op_outsig_size = GetSize(op_outsig); + int op_conn_width = 0; + + while (mux_port_offset + op_conn_width < mux_port_size && + op_outsig_offset + op_conn_width < op_outsig_size && + mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width]) + op_conn_width++; + + log_assert(op_conn_width >= 1); + + bool skip = false; + for (int i = 0; i < op_outsig_size; i++) { + int expected = 1; + if (i >= op_outsig_offset && i < op_outsig_offset + op_conn_width) + expected = 2; + if (bit_users[op_outsig[i]] != expected) + skip = true; + } + if (skip) { + mux_port_offset += op_conn_width; + mux_port_offset--; + continue; + } + + OpMuxConn inp = { + op_outsig.extract(op_outsig_offset, op_conn_width), + mux, + cell, + mux_port_id, + mux_port_offset, + op_outsig_offset, + }; + + mux_port_conns[mux_port_id].insert(inp); + + mux_port_offset += op_conn_width; + mux_port_offset--; - RTLIL::Cell* cell = val.first; - auto &mux_port_conns = val.second; + found++; + } + } + + if (found < 2) + continue; const OpMuxConn *seed = NULL; @@ -612,12 +527,12 @@ struct OptSharePass : public Pass { continue; // Filter mergeable connections whose ops share an operand with seed connection's op - auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users); + auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users, sigmap); if (shared_operand.empty()) continue; - check_muxed_operands(mergeable_conns, shared_operand); + check_muxed_operands(mergeable_conns, shared_operand, sigmap); if (mergeable_conns.size() < 2) continue; @@ -631,7 +546,7 @@ struct OptSharePass : public Pass { seed = NULL; - merged_ops.push_back(merged_op_t{cell, merged_ports, shared_operand}); + merged_ops.push_back(merged_op_t{mux, merged_ports, shared_operand}); design->scratchpad_set_bool("opt.did_something", true); } @@ -647,7 +562,7 @@ struct OptSharePass : public Pass { log(" %s\n", log_id(op.op)); log("\n"); - merge_operators(module, shared.mux, shared.ports, shared.shared_operand); + merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap); } } } diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 1a57bef7d..c6bbc386a 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -36,7 +36,6 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h)) PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg -PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index c16b4486d..a9c62fcf6 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -67,8 +67,6 @@ struct PeepoptPass : public Pass { GENERATE_PATTERN(peepopt_pm, shiftmul); else if (genmode == "muldiv") GENERATE_PATTERN(peepopt_pm, muldiv); - else if (genmode == "dffmux") - GENERATE_PATTERN(peepopt_pm, dffmux); else log_abort(); return; @@ -106,7 +104,6 @@ struct PeepoptPass : public Pass { pm.run_shiftmul(); pm.run_muldiv(); - pm.run_dffmux(); for (auto w : module->wires()) { auto it = w->attributes.find(ID::init); diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg deleted file mode 100644 index 0069b0570..000000000 --- a/passes/pmgen/peepopt_dffmux.pmg +++ /dev/null @@ -1,171 +0,0 @@ -pattern dffmux - -state <IdString> cemuxAB rstmuxBA -state <SigSpec> sigD - -match dff - select dff->type == $dff - select GetSize(port(dff, \D)) > 1 -endmatch - -code sigD - sigD = port(dff, \D); -endcode - -match rstmux - select rstmux->type == $mux - select GetSize(port(rstmux, \Y)) > 1 - index <SigSpec> port(rstmux, \Y) === sigD - choice <IdString> BA {\B, \A} - select port(rstmux, BA).is_fully_const() - set rstmuxBA BA - semioptional -endmatch - -code sigD - if (rstmux) - sigD = port(rstmux, rstmuxBA == \B ? \A : \B); -endcode - -match cemux - select cemux->type == $mux - select GetSize(port(cemux, \Y)) > 1 - index <SigSpec> port(cemux, \Y) === sigD - choice <IdString> AB {\A, \B} - index <SigSpec> port(cemux, AB) === port(dff, \Q) - set cemuxAB AB - semioptional -endmatch - -code - if (!cemux && !rstmux) - reject; -endcode - -code - Const rst; - SigSpec D; - if (cemux) { - D = port(cemux, cemuxAB == \A ? \B : \A); - if (rstmux) - rst = port(rstmux, rstmuxBA).as_const(); - else - rst = Const(State::Sx, GetSize(D)); - } - else { - log_assert(rstmux); - D = port(rstmux, rstmuxBA == \B ? \A : \B); - rst = port(rstmux, rstmuxBA).as_const(); - } - SigSpec Q = port(dff, \Q); - int width = GetSize(D); - - SigSpec dffD = dff->getPort(\D); - SigSpec dffQ = dff->getPort(\Q); - - Const initval; - for (auto b : Q) { - auto it = initbits.find(b); - initval.bits.push_back(it == initbits.end() ? State::Sx : it->second); - } - - auto cmpx = [=](State lhs, State rhs) { - if (lhs == State::Sx || rhs == State::Sx) - return true; - return lhs == rhs; - }; - - int i = width-1; - while (i > 1) { - if (D[i] != D[i-1]) - break; - if (!cmpx(rst[i], rst[i-1])) - break; - if (!cmpx(initval[i], initval[i-1])) - break; - if (!cmpx(rst[i], initval[i])) - break; - rminitbits.insert(Q[i]); - module->connect(Q[i], Q[i-1]); - i--; - } - if (i < width-1) { - did_something = true; - if (cemux) { - SigSpec ceA = cemux->getPort(\A); - SigSpec ceB = cemux->getPort(\B); - SigSpec ceY = cemux->getPort(\Y); - ceA.remove(i, width-1-i); - ceB.remove(i, width-1-i); - ceY.remove(i, width-1-i); - cemux->setPort(\A, ceA); - cemux->setPort(\B, ceB); - cemux->setPort(\Y, ceY); - cemux->fixup_parameters(); - blacklist(cemux); - } - if (rstmux) { - SigSpec rstA = rstmux->getPort(\A); - SigSpec rstB = rstmux->getPort(\B); - SigSpec rstY = rstmux->getPort(\Y); - rstA.remove(i, width-1-i); - rstB.remove(i, width-1-i); - rstY.remove(i, width-1-i); - rstmux->setPort(\A, rstA); - rstmux->setPort(\B, rstB); - rstmux->setPort(\Y, rstY); - rstmux->fixup_parameters(); - blacklist(rstmux); - } - dffD.remove(i, width-1-i); - dffQ.remove(i, width-1-i); - dff->setPort(\D, dffD); - dff->setPort(\Q, dffQ); - dff->fixup_parameters(); - blacklist(dff); - - log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i); - width = i+1; - } - if (cemux) { - SigSpec ceA = cemux->getPort(\A); - SigSpec ceB = cemux->getPort(\B); - SigSpec ceY = cemux->getPort(\Y); - - int count = 0; - for (int i = width-1; i >= 0; i--) { - if (D[i].wire) - continue; - if (cmpx(rst[i], D[i].data) && cmpx(initval[i], D[i].data)) { - count++; - rminitbits.insert(Q[i]); - module->connect(Q[i], D[i]); - ceA.remove(i); - ceB.remove(i); - ceY.remove(i); - dffD.remove(i); - dffQ.remove(i); - } - } - if (count > 0) - { - did_something = true; - - cemux->setPort(\A, ceA); - cemux->setPort(\B, ceB); - cemux->setPort(\Y, ceY); - cemux->fixup_parameters(); - blacklist(cemux); - - dff->setPort(\D, dffD); - dff->setPort(\Q, dffQ); - dff->fixup_parameters(); - blacklist(dff); - - log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count); - } - } - - if (did_something) - accept; -endcode diff --git a/passes/pmgen/peepopt_muldiv.pmg b/passes/pmgen/peepopt_muldiv.pmg index 7cad759d0..a4e232342 100644 --- a/passes/pmgen/peepopt_muldiv.pmg +++ b/passes/pmgen/peepopt_muldiv.pmg @@ -1,16 +1,18 @@ pattern muldiv state <SigSpec> t x y +state <bool> is_signed match mul select mul->type == $mul select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y)) endmatch -code t x y +code t x y is_signed t = port(mul, \Y); x = port(mul, \A); y = port(mul, \B); + is_signed = param(mul, \A_SIGNED).as_bool(); branch; std::swap(x, y); endcode @@ -19,6 +21,7 @@ match div select div->type.in($div) index <SigSpec> port(div, \A) === t index <SigSpec> port(div, \B) === x + filter param(div, \A_SIGNED).as_bool() == is_signed endmatch code diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg index d4748ae19..d71fbf744 100644 --- a/passes/pmgen/peepopt_shiftmul.pmg +++ b/passes/pmgen/peepopt_shiftmul.pmg @@ -31,22 +31,18 @@ match mul select mul->type.in($mul) select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const() index <SigSpec> port(mul, \Y) === shamt + filter !param(mul, \A_SIGNED).as_bool() endmatch code { IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B; - IdString const_factor_signed = const_factor_port == \A ? \A_SIGNED : \B_SIGNED; Const const_factor_cnst = port(mul, const_factor_port).as_const(); int const_factor = const_factor_cnst.as_int(); if (GetSize(const_factor_cnst) == 0) reject; - if (const_factor_cnst.bits[GetSize(const_factor_cnst)-1] != State::S0 && - param(mul, const_factor_signed).as_bool()) - reject; - if (GetSize(const_factor_cnst) > 20) reject; diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index f20a167b4..09cf0af82 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -50,6 +50,9 @@ struct ProcPass : public Pass { log("\n"); log("The following options are supported:\n"); log("\n"); + log(" -nomux\n"); + log(" Will omit the proc_mux pass.\n"); + log("\n"); log(" -global_arst [!]<netname>\n"); log(" This option is passed through to proc_arst.\n"); log("\n"); @@ -62,6 +65,7 @@ struct ProcPass : public Pass { { std::string global_arst; bool ifxmode = false; + bool nomux = false; log_header(design, "Executing PROC pass (convert processes to netlists).\n"); log_push(); @@ -69,6 +73,10 @@ struct ProcPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } if (args[argidx] == "-global_arst" && argidx+1 < args.size()) { global_arst = args[++argidx]; continue; @@ -90,7 +98,8 @@ struct ProcPass : public Pass { Pass::call(design, "proc_arst"); else Pass::call(design, "proc_arst -global_arst " + global_arst); - Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); + if (!nomux) + Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); Pass::call(design, "proc_dlatch"); Pass::call(design, "proc_dff"); Pass::call(design, "proc_clean"); diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 5a4d84f94..035699603 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -27,7 +27,6 @@ OBJS += passes/techmap/extract_fa.o OBJS += passes/techmap/extract_counter.o OBJS += passes/techmap/extract_reduce.o OBJS += passes/techmap/alumacc.o -OBJS += passes/techmap/dff2dffe.o OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/muxcover.o @@ -42,7 +41,6 @@ OBJS += passes/techmap/attrmvcp.o OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dfflegalize.o -OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/dffunmap.o OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index e99c56d8d..7d017ac40 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -295,7 +295,7 @@ struct Abc9Pass : public ScriptPass run("proc"); run("wbflip"); run("techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop"); - run("opt"); + run("opt -nodffe -nosdff"); if (dff_mode || help_mode) { if (!help_mode) active_design->scratchpad_unset("abc9_ops.prep_dff_submod.did_something"); diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc deleted file mode 100644 index 62ee3fea6..000000000 --- a/passes/techmap/dff2dffe.cc +++ /dev/null @@ -1,414 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "kernel/celltypes.h" -#include "passes/techmap/simplemap.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct Dff2dffeWorker -{ - const dict<IdString, IdString> &direct_dict; - - RTLIL::Module *module; - SigMap sigmap; - CellTypes ct; - - typedef std::pair<RTLIL::Cell*, int> cell_int_t; - std::map<RTLIL::SigBit, cell_int_t> bit2mux; - std::vector<RTLIL::Cell*> dff_cells; - std::map<RTLIL::SigBit, int> bitusers; - - typedef std::map<RTLIL::SigBit, bool> pattern_t; - typedef std::set<pattern_t> patterns_t; - - - Dff2dffeWorker(RTLIL::Module *module, const dict<IdString, IdString> &direct_dict) : - direct_dict(direct_dict), module(module), sigmap(module), ct(module->design) - { - for (auto wire : module->wires()) { - if (wire->port_output) - for (auto bit : sigmap(wire)) - bitusers[bit]++; - } - - for (auto cell : module->cells()) { - if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) { - RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); - for (int i = 0; i < GetSize(sig_y); i++) - bit2mux[sig_y[i]] = cell_int_t(cell, i); - } - if (direct_dict.empty()) { - if (cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) - dff_cells.push_back(cell); - } else { - if (direct_dict.count(cell->type)) - dff_cells.push_back(cell); - } - for (auto conn : cell->connections()) { - if (ct.cell_output(cell->type, conn.first)) - continue; - for (auto bit : sigmap(conn.second)) - bitusers[bit]++; - } - } - } - - patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path) - { - patterns_t ret; - - if (d == q) { - ret.insert(path); - return ret; - } - - if (bit2mux.count(d) == 0 || bitusers[d] > 1) - return ret; - - cell_int_t mux_cell_int = bit2mux.at(d); - RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A)); - RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B)); - RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID::S)); - int width = GetSize(sig_a), index = mux_cell_int.second; - - for (int i = 0; i < GetSize(sig_s); i++) - if (path.count(sig_s[i]) && path.at(sig_s[i])) - { - ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path); - - if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B); - s[i*width + index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::B, s); - } - - return ret; - } - - pattern_t path_else = path; - - for (int i = 0; i < GetSize(sig_s); i++) - { - if (path.count(sig_s[i])) - continue; - - pattern_t path_this = path; - path_else[sig_s[i]] = false; - path_this[sig_s[i]] = true; - - for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this)) - ret.insert(pat); - - if (sig_b[i*width + index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::B); - s[i*width + index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::B, s); - } - } - - for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else)) - ret.insert(pat); - - if (sig_a[index] == q) { - RTLIL::SigSpec s = mux_cell_int.first->getPort(ID::A); - s[index] = RTLIL::Sx; - mux_cell_int.first->setPort(ID::A, s); - } - - return ret; - } - - void simplify_patterns(patterns_t&) - { - // TBD - } - - RTLIL::SigSpec make_patterns_logic(patterns_t patterns, bool make_gates) - { - RTLIL::SigSpec or_input; - - for (auto pat : patterns) - { - RTLIL::SigSpec s1, s2; - for (auto it : pat) { - s1.append(it.first); - s2.append(it.second); - } - - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - - or_input.append(y); - } - - if (GetSize(or_input) == 0) - return State::S1; - - if (GetSize(or_input) == 1) - return or_input; - - RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); - - if (make_gates) { - simplemap(module, c); - module->remove(c); - } - - return y; - } - - void handle_dff_cell(RTLIL::Cell *dff_cell) - { - RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID::D)); - RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID::Q)); - - std::map<patterns_t, std::set<int>> grouped_patterns; - std::set<int> remaining_indices; - - for (int i = 0 ; i < GetSize(sig_d); i++) { - patterns_t patterns = find_muxtree_feedback_patterns(sig_d[i], sig_q[i], pattern_t()); - if (!patterns.empty()) { - simplify_patterns(patterns); - grouped_patterns[patterns].insert(i); - } else - remaining_indices.insert(i); - } - - for (auto &it : grouped_patterns) { - RTLIL::SigSpec new_sig_d, new_sig_q; - for (int i : it.second) { - new_sig_d.append(sig_d[i]); - new_sig_q.append(sig_q[i]); - } - if (!direct_dict.empty()) { - log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q)); - dff_cell->setPort(ID::E, make_patterns_logic(it.first, true)); - dff_cell->type = direct_dict.at(dff_cell->type); - } else - if (dff_cell->type == ID($dff)) { - RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID::CLK), make_patterns_logic(it.first, false), - new_sig_d, new_sig_q, dff_cell->getParam(ID::CLK_POLARITY).as_bool(), true); - log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); - } else { - RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID::C), make_patterns_logic(it.first, true), - new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true); - log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q)); - } - } - - if (!direct_dict.empty()) - return; - - if (remaining_indices.empty()) { - log(" removing now obsolete cell %s.\n", log_id(dff_cell)); - module->remove(dff_cell); - } else if (GetSize(remaining_indices) != GetSize(sig_d)) { - log(" removing %d now obsolete bits from cell %s.\n", GetSize(sig_d) - GetSize(remaining_indices), log_id(dff_cell)); - RTLIL::SigSpec new_sig_d, new_sig_q; - for (int i : remaining_indices) { - new_sig_d.append(sig_d[i]); - new_sig_q.append(sig_q[i]); - } - dff_cell->setPort(ID::D, new_sig_d); - dff_cell->setPort(ID::Q, new_sig_q); - dff_cell->setParam(ID::WIDTH, GetSize(remaining_indices)); - } - } - - void run() - { - log("Transforming FF to FF+Enable cells in module %s:\n", log_id(module)); - for (auto dff_cell : dff_cells) { - // log("Handling candidate %s:\n", log_id(dff_cell)); - handle_dff_cell(dff_cell); - } - } -}; - -struct Dff2dffePass : public Pass { - Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" dff2dffe [options] [selection]\n"); - log("\n"); - log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n"); - log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n"); - log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n"); - log("\n"); - log(" -unmap\n"); - log(" operate in the opposite direction: replace $dffe cells with combinations\n"); - log(" of $dff and $mux cells. the options below are ignored in unmap mode.\n"); - log("\n"); - log(" -unmap-mince N\n"); - log(" Same as -unmap but only unmap $dffe where the clock enable port\n"); - log(" signal is used by less $dffe than the specified number\n"); - log("\n"); - log(" -direct <internal_gate_type> <external_gate_type>\n"); - log(" map directly to external gate type. <internal_gate_type> can\n"); - log(" be any internal gate-level FF cell (except $_DFFE_??_). the\n"); - log(" <external_gate_type> is the cell type name for a cell with an\n"); - log(" identical interface to the <internal_gate_type>, except it\n"); - log(" also has an high-active enable port 'E'.\n"); - log(" Usually <external_gate_type> is an intermediate cell type\n"); - log(" that is then translated to the final type using 'techmap'.\n"); - log("\n"); - log(" -direct-match <pattern>\n"); - log(" like -direct for all DFF cell types matching the expression.\n"); - log(" this will use $_DFFE_* as <external_gate_type> matching the\n"); - log(" internal gate type $_DFF_*_, and $_SDFFE_* for those matching\n"); - log(" $_SDFF_*_, except for $_DFF_[NP]_, which is converted to \n"); - log(" $_DFFE_[NP]_.\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n"); - - bool unmap_mode = false; - int min_ce_use = -1; - dict<IdString, IdString> direct_dict; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-unmap") { - unmap_mode = true; - continue; - } - if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) { - unmap_mode = true; - min_ce_use = atoi(args[++argidx].c_str()); - continue; - } - if (args[argidx] == "-direct" && argidx + 2 < args.size()) { - string direct_from = RTLIL::escape_id(args[++argidx]); - string direct_to = RTLIL::escape_id(args[++argidx]); - direct_dict[direct_from] = direct_to; - continue; - } - if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) { - bool found_match = false; - const char *pattern = args[++argidx].c_str(); - if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict[ID($_DFF_P_) ] = ID($_DFFE_PP_); - if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict[ID($_DFF_N_) ] = ID($_DFFE_NP_); - if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($_DFFE_NN0P_); - if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($_DFFE_NN1P_); - if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($_DFFE_NP0P_); - if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($_DFFE_NP1P_); - if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($_DFFE_PN0P_); - if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($_DFFE_PN1P_); - if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($_DFFE_PP0P_); - if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($_DFFE_PP1P_); - - if (patmatch(pattern, "$_SDFF_NN0_")) found_match = true, direct_dict[ID($_SDFF_NN0_)] = ID($_SDFFE_NN0P_); - if (patmatch(pattern, "$_SDFF_NN1_")) found_match = true, direct_dict[ID($_SDFF_NN1_)] = ID($_SDFFE_NN1P_); - if (patmatch(pattern, "$_SDFF_NP0_")) found_match = true, direct_dict[ID($_SDFF_NP0_)] = ID($_SDFFE_NP0P_); - if (patmatch(pattern, "$_SDFF_NP1_")) found_match = true, direct_dict[ID($_SDFF_NP1_)] = ID($_SDFFE_NP1P_); - if (patmatch(pattern, "$_SDFF_PN0_")) found_match = true, direct_dict[ID($_SDFF_PN0_)] = ID($_SDFFE_PN0P_); - if (patmatch(pattern, "$_SDFF_PN1_")) found_match = true, direct_dict[ID($_SDFF_PN1_)] = ID($_SDFFE_PN1P_); - if (patmatch(pattern, "$_SDFF_PP0_")) found_match = true, direct_dict[ID($_SDFF_PP0_)] = ID($_SDFFE_PP0P_); - if (patmatch(pattern, "$_SDFF_PP1_")) found_match = true, direct_dict[ID($_SDFF_PP1_)] = ID($_SDFFE_PP1P_); - if (!found_match) - log_cmd_error("No cell types matched pattern '%s'.\n", pattern); - continue; - } - break; - } - extra_args(args, argidx, design); - - if (!direct_dict.empty()) { - log("Selected cell types for direct conversion:\n"); - for (auto &it : direct_dict) - log(" %s -> %s\n", log_id(it.first), log_id(it.second)); - } - - for (auto mod : design->selected_modules()) - if (!mod->has_processes_warn()) - { - if (unmap_mode) { - SigMap sigmap(mod); - for (auto cell : mod->selected_cells()) { - if (cell->type == ID($dffe)) { - if (min_ce_use >= 0) { - int ce_use = 0; - for (auto cell_other : mod->selected_cells()) { - if (cell_other->type != cell->type) - continue; - if (sigmap(cell->getPort(ID::EN)) == sigmap(cell_other->getPort(ID::EN))) - ce_use++; - } - if (ce_use >= min_ce_use) - continue; - } - - RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID::D))); - mod->addDff(NEW_ID, cell->getPort(ID::CLK), tmp, cell->getPort(ID::Q), cell->getParam(ID::CLK_POLARITY).as_bool()); - if (cell->getParam(ID::EN_POLARITY).as_bool()) - mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::EN), tmp); - else - mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::EN), tmp); - mod->remove(cell); - continue; - } - if (cell->type.begins_with("$_DFFE_")) { - if (min_ce_use >= 0) { - int ce_use = 0; - for (auto cell_other : mod->selected_cells()) { - if (cell_other->type != cell->type) - continue; - if (sigmap(cell->getPort(ID::E)) == sigmap(cell_other->getPort(ID::E))) - ce_use++; - } - if (ce_use >= min_ce_use) - continue; - } - - bool clk_pol = cell->type.compare(7, 1, "P") == 0; - bool en_pol = cell->type.compare(8, 1, "P") == 0; - RTLIL::SigSpec tmp = mod->addWire(NEW_ID); - mod->addDff(NEW_ID, cell->getPort(ID::C), tmp, cell->getPort(ID::Q), clk_pol); - if (en_pol) - mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::E), tmp); - else - mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::E), tmp); - mod->remove(cell); - continue; - } - } - continue; - } - - Dff2dffeWorker worker(mod, direct_dict); - worker.run(); - } - } -} Dff2dffePass; - -PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc deleted file mode 100644 index 6c2cca4bc..000000000 --- a/passes/techmap/dff2dffs.cc +++ /dev/null @@ -1,165 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * Copyright (C) 2018 David Shah <dave@ds0.me> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct Dff2dffsPass : public Pass { - Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { } - void help() override - { - log("\n"); - log(" dff2dffs [options] [selection]\n"); - log("\n"); - log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n"); - log("dff2dffe for SR over CE priority.\n"); - log("\n"); - log(" -match-init\n"); - log(" Disallow merging synchronous set/reset that has polarity opposite of the\n"); - log(" output wire's init attribute (if any).\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) override - { - log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); - - bool match_init = false; - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - // if (args[argidx] == "-singleton") { - // singleton_mode = true; - // continue; - // } - if (args[argidx] == "-match-init") { - match_init = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - pool<IdString> dff_types; - dff_types.insert(ID($_DFF_N_)); - dff_types.insert(ID($_DFF_P_)); - - for (auto module : design->selected_modules()) - { - log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module)); - - SigMap sigmap(module); - dict<SigBit, Cell*> sr_muxes; - vector<Cell*> ff_cells; - - for (auto cell : module->selected_cells()) - { - if (dff_types.count(cell->type)) { - ff_cells.push_back(cell); - continue; - } - - if (cell->type != ID($_MUX_)) - continue; - - SigBit bit_a = sigmap(cell->getPort(ID::A)); - SigBit bit_b = sigmap(cell->getPort(ID::B)); - - if (bit_a.wire == nullptr || bit_b.wire == nullptr) - sr_muxes[sigmap(cell->getPort(ID::Y))] = cell; - } - - for (auto cell : ff_cells) - { - SigSpec sig_d = cell->getPort(ID::D); - - if (GetSize(sig_d) < 1) - continue; - - SigBit bit_d = sigmap(sig_d[0]); - - if (sr_muxes.count(bit_d) == 0) - continue; - - Cell *mux_cell = sr_muxes.at(bit_d); - SigBit bit_a = sigmap(mux_cell->getPort(ID::A)); - SigBit bit_b = sigmap(mux_cell->getPort(ID::B)); - SigBit bit_s = sigmap(mux_cell->getPort(ID::S)); - - SigBit sr_val, sr_sig; - bool invert_sr; - sr_sig = bit_s; - if (bit_a.wire == nullptr) { - bit_d = bit_b; - sr_val = bit_a; - invert_sr = true; - } else { - log_assert(bit_b.wire == nullptr); - bit_d = bit_a; - sr_val = bit_b; - invert_sr = false; - } - - if (match_init) { - SigBit bit_q = cell->getPort(ID::Q); - if (bit_q.wire) { - auto it = bit_q.wire->attributes.find(ID::init); - if (it != bit_q.wire->attributes.end()) { - auto init_val = it->second[bit_q.offset]; - if (init_val == State::S1 && sr_val != State::S1) - continue; - if (init_val == State::S0 && sr_val != State::S0) - continue; - } - } - } - - log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), - log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); - - if (sr_val == State::S1) { - if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($_SDFF_NN1_); - else cell->type = ID($_SDFF_NP1_); - } else { - log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($_SDFF_PN1_); - else cell->type = ID($_SDFF_PP1_); - } - } else { - if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($_SDFF_NN0_); - else cell->type = ID($_SDFF_NP0_); - } else { - log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($_SDFF_PN0_); - else cell->type = ID($_SDFF_PP0_); - } - } - cell->setPort(ID::R, sr_sig); - cell->setPort(ID::D, bit_d); - } - } - } -} Dff2dffsPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 8ad65493f..c1e7e557d 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -418,7 +418,8 @@ unmap_enable: ff_type = has_set ? FF_ADFFE1 : FF_ADFFE0; break; } - if (supported_dffsr & initmask) { + if (supported_cells[has_en ? FF_DFFSRE : FF_DFFSR] & initmask) { +adff_to_dffsr: // Throw in a set/reset, retry in DFFSR/DFFSRE branch. if (has_set) { sig_s = sig_r; @@ -441,6 +442,9 @@ unmap_enable: ff_type = has_set ? FF_ADFF1 : FF_ADFF0; goto unmap_enable; } + if (supported_dffsr & initmask) { + goto adff_to_dffsr; + } log_assert(!((has_set ? supported_adff1 : supported_adff0) & initmask)); // Alright, so this particular combination of initval and // resetval is not natively supported. First, try flipping diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 7278cb680..f5966fac0 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -354,7 +354,7 @@ struct ExtractPass : public Pass { log("\n"); log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n"); + log("map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).\n"); log("\n"); log(" -map <map_file>\n"); log(" use the modules in this file as reference. This option can be used\n"); @@ -409,7 +409,7 @@ struct ExtractPass : public Pass { log("the following options are to be used instead of the -map option.\n"); log("\n"); log(" -mine <out_file>\n"); - log(" mine for frequent subcircuits and write them to the given ilang file\n"); + log(" mine for frequent subcircuits and write them to the given RTLIL file\n"); log("\n"); log(" -mine_cells_span <min> <max>\n"); log(" only mine for subcircuits with the specified number of cells\n"); @@ -578,7 +578,7 @@ struct ExtractPass : public Pass { } if (map_filenames.empty() && mine_outfile.empty()) - log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n"); + log_cmd_error("Missing option -map <verilog_or_rtlil_file> or -mine <output_rtlil_file>.\n"); RTLIL::Design *map = nullptr; @@ -606,7 +606,7 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); } - Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); f.close(); if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) { @@ -744,7 +744,7 @@ struct ExtractPass : public Pass { f.open(mine_outfile.c_str(), std::ofstream::trunc); if (f.fail()) log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); - Backend::backend_call(map, &f, mine_outfile, "ilang"); + Backend::backend_call(map, &f, mine_outfile, "rtlil"); f.close(); } diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index b5f55cffa..08978f446 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -152,15 +152,14 @@ struct FlattenWorker // Attach port connections of the flattened cell - SigMap tpl_sigmap(tpl); pool<SigBit> tpl_driven; for (auto tpl_cell : tpl->cells()) for (auto &tpl_conn : tpl_cell->connections()) if (tpl_cell->output(tpl_conn.first)) - for (auto bit : tpl_sigmap(tpl_conn.second)) + for (auto bit : tpl_conn.second) tpl_driven.insert(bit); for (auto &tpl_conn : tpl->connections()) - for (auto bit : tpl_sigmap(tpl_conn.first)) + for (auto bit : tpl_conn.first) tpl_driven.insert(bit); SigMap sigmap(module); @@ -190,7 +189,7 @@ struct FlattenWorker } else { SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { - if (tpl_driven.count(tpl_sigmap(sig_tpl[i]))) { + if (tpl_driven.count(sig_tpl[i])) { new_conn.first.append(sig_mod[i]); new_conn.second.append(sig_tpl[i]); } else { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c22ae8ef0..d43737c8d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -233,16 +233,14 @@ struct TechmapWorker } } - SigMap tpl_sigmap(tpl); pool<SigBit> tpl_written_bits; - for (auto tpl_cell : tpl->cells()) for (auto &conn : tpl_cell->connections()) if (tpl_cell->output(conn.first)) - for (auto bit : tpl_sigmap(conn.second)) + for (auto bit : conn.second) tpl_written_bits.insert(bit); for (auto &conn : tpl->connections()) - for (auto bit : tpl_sigmap(conn.first)) + for (auto bit : conn.first) tpl_written_bits.insert(bit); SigMap port_signal_map; @@ -280,7 +278,7 @@ struct TechmapWorker SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; apply_prefix(cell->name, sig_tpl_pf, module); for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { - if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) { + if (tpl_written_bits.count(sig_tpl[i])) { c.first.append(sig_mod[i]); c.second.append(sig_tpl_pf[i]); } else { @@ -801,11 +799,31 @@ struct TechmapWorker } } + // Handle outputs first, as these cannot be remapped. + for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (!twire->port_output) + continue; + + for (int i = 0; i < GetSize(conn.second); i++) { + RTLIL::SigBit bit = sigmap(conn.second[i]); + RTLIL::SigBit tplbit(twire, i); + cellbits_to_tplbits[bit] = tplbit; + } + } + + // Now handle inputs, remapping as necessary. for (auto &conn : cell->connections()) + { + Wire *twire = tpl->wire(conn.first); + if (twire->port_output) + continue; + for (int i = 0; i < GetSize(conn.second); i++) { RTLIL::SigBit bit = sigmap(conn.second[i]); - RTLIL::SigBit tplbit(tpl->wire(conn.first), i); + RTLIL::SigBit tplbit(twire, i); if (bit.wire == nullptr) { @@ -820,6 +838,7 @@ struct TechmapWorker else cellbits_to_tplbits[bit] = tplbit; } + } RTLIL::SigSig port_conn; for (auto &it : port_connmap) { @@ -964,7 +983,7 @@ struct TechmapPass : public Pass { log(" techmap [-map filename] [selection]\n"); log("\n"); log("This pass implements a very simple technology mapper that replaces cells in\n"); - log("the design with implementations given in form of a Verilog or ilang source\n"); + log("the design with implementations given in form of a Verilog or RTLIL source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); @@ -1007,7 +1026,9 @@ struct TechmapPass : public Pass { log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); - log("the module name will be used to match the cell.\n"); + log("the module name will be used to match the cell. Multiple space-separated cell\n"); + log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n"); + log("is the same as \"$_DFF_P_ $_DFF_N_\").\n"); log("\n"); log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n"); log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n"); @@ -1189,7 +1210,7 @@ struct TechmapPass : public Pass { if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } @@ -1199,8 +1220,27 @@ struct TechmapPass : public Pass { for (auto module : map->modules()) { if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); - for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) - celltypeMap[RTLIL::escape_id(q)].insert(module->name); + for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) { + std::vector<std::string> queue; + queue.push_back(q); + while (!queue.empty()) { + std::string name = queue.back(); + queue.pop_back(); + auto pos = name.find('['); + if (pos == std::string::npos) { + // No further expansion. + celltypeMap[RTLIL::escape_id(name)].insert(module->name); + } else { + // Expand [] in this name. + auto epos = name.find(']', pos); + if (epos == std::string::npos) + log_error("Malformed techmap_celltype pattern %s\n", q); + for (size_t i = pos + 1; i < epos; i++) { + queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos)); + } + } + } + } free(p); } else { IdString module_name = module->name.begins_with("\\$") ? @@ -1208,8 +1248,15 @@ struct TechmapPass : public Pass { celltypeMap[module_name].insert(module->name); } } - for (auto &i : celltypeMap) + log_debug("Cell type mappings to use:\n"); + for (auto &i : celltypeMap) { i.second.sort(RTLIL::sort_by_id_str()); + std::string maps = ""; + for (auto &map : i.second) + maps += stringf(" %s", log_id(map)); + log_debug(" %s:%s\n", log_id(i.first), maps.c_str()); + } + log_debug("\n"); for (auto module : design->modules()) worker.module_queue.insert(module); diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 2d80e66e4..ac31e36f1 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -171,7 +171,7 @@ static void test_abcloop() } log("Found viable UUT after %d cycles:\n", create_cycles); - Pass::call(design, "write_ilang"); + Pass::call(design, "write_rtlil"); Pass::call(design, "abc"); log("\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index bdb475d3b..616981f32 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } + if (cell_type.in(ID($shiftx))) { + cell->parameters[ID::A_SIGNED] = false; + } + if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { cell->parameters[ID::B_SIGNED] = false; } @@ -674,12 +678,12 @@ struct TestCellPass : public Pass { log(" -s {positive_integer}\n"); log(" use this value as rng seed value (default = unix time).\n"); log("\n"); - log(" -f {ilang_file}\n"); - log(" don't generate circuits. instead load the specified ilang file.\n"); + log(" -f {rtlil_file}\n"); + log(" don't generate circuits. instead load the specified RTLIL file.\n"); log("\n"); log(" -w {filename_prefix}\n"); log(" don't test anything. just generate the circuits and write them\n"); - log(" to ilang files with the specified prefix\n"); + log(" to RTLIL files with the specified prefix\n"); log("\n"); log(" -map {filename}\n"); log(" pass this option to techmap.\n"); @@ -720,7 +724,7 @@ struct TestCellPass : public Pass { { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; - std::string ilang_file, write_prefix; + std::string rtlil_file, write_prefix; xorshift32_state = 0; std::ofstream vlog_file; bool muxdiv = false; @@ -746,7 +750,7 @@ struct TestCellPass : public Pass { continue; } if (args[argidx] == "-f" && argidx+1 < GetSize(args)) { - ilang_file = args[++argidx]; + rtlil_file = args[++argidx]; num_iter = 1; continue; } @@ -906,10 +910,10 @@ struct TestCellPass : public Pass { selected_cell_types.push_back(args[argidx]); } - if (!ilang_file.empty()) { + if (!rtlil_file.empty()) { if (!selected_cell_types.empty()) log_cmd_error("Do not specify any cell types when using -f.\n"); - selected_cell_types.push_back(ID(ilang)); + selected_cell_types.push_back(ID(rtlil)); } if (selected_cell_types.empty()) @@ -921,12 +925,12 @@ struct TestCellPass : public Pass { for (int i = 0; i < num_iter; i++) { RTLIL::Design *design = new RTLIL::Design; - if (cell_type == ID(ilang)) - Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); + if (cell_type == ID(rtlil)) + Frontend::frontend_call(design, NULL, std::string(), "rtlil " + rtlil_file); else create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); if (!write_prefix.empty()) { - Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); + Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); } else if (edges) { Pass::call(design, "dump gold"); run_edges_test(design, verbose); diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v index 6ed90b5f5..b00e0e6a8 100644 --- a/techlibs/common/abc9_map.v +++ b/techlibs/common/abc9_map.v @@ -1,5 +1,5 @@ `ifdef DFF -(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *) +(* techmap_celltype = "$_DFF_[PN]_" *) module $_DFF_x_(input C, D, output Q); parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; parameter _TECHMAP_CELLTYPE_ = ""; diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2660e6f15..e94884025 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -480,10 +480,18 @@ input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate - if (B_SIGNED) begin:BLOCK1 - assign Y = $signed(B) < 0 ? A << -B : A >> B; - end else begin:BLOCK2 - assign Y = A >> B; + if (A_SIGNED) begin:BLOCK1 + if (B_SIGNED) begin:BLOCK2 + assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B; + end else begin:BLOCK3 + assign Y = $signed(A) >> B; + end + end else begin:BLOCK4 + if (B_SIGNED) begin:BLOCK5 + assign Y = $signed(B) < 0 ? A << -B : A >> B; + end else begin:BLOCK6 + assign Y = A >> B; + end end endgenerate diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index b4c65e658..89d6e530e 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -220,6 +220,9 @@ struct SynthPass : public ScriptPass run("opt_expr"); run("opt_clean"); run("check"); + run("opt -nodffe -nosdff"); + if (!nofsm) + run("fsm" + fsm_opts, " (unless -nofsm)"); run("opt"); run("wreduce"); run("peepopt"); @@ -233,9 +236,6 @@ struct SynthPass : public ScriptPass if (!noshare) run("share", " (unless -noshare)"); run("opt"); - if (!nofsm) - run("fsm" + fsm_opts, " (unless -nofsm)"); - run("opt -fast"); run("memory -nomap" + memory_opts); run("opt_clean"); } diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 9607302b7..2ab28e6e6 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -141,78 +141,48 @@ module _90_shift_shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx; + wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0); - generate -`ifndef NO_LSB_FIRST_SHIFT_SHIFTX - // If $shift/$shiftx only shifts in units of Y_WIDTH - // (a common pattern created by pmux2shiftx) - // which is checked by ensuring that all that - // the appropriate LSBs of B are constant zero, - // then we can decompose LSB first instead of - // MSB first - localparam CLOG2_Y_WIDTH = $clog2(Y_WIDTH); - if (B_WIDTH > CLOG2_Y_WIDTH+1 && - _TECHMAP_CONSTMSK_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b1}} && - _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin - // Halve the size of $shift/$shiftx by $mux-ing A according to - // the LSB of B, after discarding the zeroed bits - localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; - localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2; - localparam len = Y_WIDTH2 * ((entries+1)/2); - wire [len-1:0] AA; - wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A}; - genvar i; - for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) - assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2]; - wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; - if (_TECHMAP_CELLTYPE_ == "$shift") - $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); - else - $shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); - end - else -`endif - begin - localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH); - localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0); + localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH); + localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0); - wire [1023:0] _TECHMAP_DO_00_ = "proc;;"; - wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; + wire [1023:0] _TECHMAP_DO_00_ = "proc;;"; + wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;"; - integer i; - (* force_downto *) - reg [WIDTH-1:0] buffer; - reg overflow; + integer i; + (* force_downto *) + reg [WIDTH-1:0] buffer; + reg overflow; - always @* begin - overflow = 0; + always @* begin + overflow = 0; + buffer = {WIDTH{extbit}}; + buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}}; + buffer[A_WIDTH-1:0] = A; + + if (B_WIDTH > BB_WIDTH) begin + if (B_SIGNED) begin + for (i = BB_WIDTH; i < B_WIDTH; i = i+1) + if (B[i] != B[BB_WIDTH-1]) + overflow = 1; + end else + overflow = |B[B_WIDTH-1:BB_WIDTH]; + if (overflow) buffer = {WIDTH{extbit}}; - buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A; - - if (B_WIDTH > BB_WIDTH) begin - if (B_SIGNED) begin - for (i = BB_WIDTH; i < B_WIDTH; i = i+1) - if (B[i] != B[BB_WIDTH-1]) - overflow = 1; - end else - overflow = |B[B_WIDTH-1:BB_WIDTH]; - if (overflow) - buffer = {WIDTH{extbit}}; - end - - for (i = BB_WIDTH-1; i >= 0; i = i-1) - if (B[i]) begin - if (B_SIGNED && i == BB_WIDTH-1) - buffer = {buffer, {2**i{extbit}}}; - else if (2**i < WIDTH) - buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]}; - else - buffer = {WIDTH{extbit}}; - end - end - assign Y = buffer; end - endgenerate + + if (B_SIGNED && B[BB_WIDTH-1]) + buffer = {buffer, {2**(BB_WIDTH-1){extbit}}}; + + for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1) + if (B[i]) begin + if (2**i < WIDTH) + buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]}; + else + buffer = {WIDTH{extbit}}; + end + end + assign Y = buffer; endmodule diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 46d051e44..3cee9722e 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -257,6 +257,8 @@ struct SynthEcp5Pass : public ScriptPass run("opt_expr"); run("opt_clean"); run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); run("opt"); run("wreduce"); run("peepopt"); @@ -271,8 +273,6 @@ struct SynthEcp5Pass : public ScriptPass } run("alumacc"); run("opt"); - run("fsm"); - run("opt -fast"); run("memory -nomap"); run("opt_clean"); } @@ -311,16 +311,20 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("map_ffs")) { - run("dff2dffs"); run("opt_clean"); - if (!nodffe) - run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*"); - if (help_mode) - run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x [-cell $_DFFSR_?PP_ x]", "($_DFFSR_*_ only if -asyncprld)"); - else if (asyncprld) - run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x -cell $_DFFSR_?PP_ x"); - else - run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFFE_??_ 01 -cell $_DFF_?P?_ r -cell $_DFFE_?P??_ r -cell $_SDFF_?P?_ r -cell $_SDFFE_?P??_ r -cell $_DLATCH_?_ x"); + std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; + if (help_mode) { + dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]"; + } else if (!nodffe) { + dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r"; + } + dfflegalize_args += " -cell $_DLATCH_?_ x"; + if (help_mode) { + dfflegalize_args += " [-cell $_DFFSR_?PP_ x]"; + } else if (asyncprld) { + dfflegalize_args += " -cell $_DFFSR_?PP_ x"; + } + run("dfflegalize" + dfflegalize_args, "($_DFFSR_*_ only if -asyncprld, $_*DFFE_* only if not -nodffe)"); if ((abc9 && dff) || help_mode) run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff"); run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : ""))); diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 3091ad196..6f6271da2 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -1,4 +1,4 @@ -(* techmap_celltype = "$_DFFE_PP0P_ $_DFFE_PP0N_ $_DFFE_PP1P_ $_DFFE_PP1N_ $_DFFE_PN0P_ $_DFFE_PN0N_ $_DFFE_PN1P_ $_DFFE_PN1N_ $_DFFE_NP0P_ $_DFFE_NP0N_ $_DFFE_NP1P_ $_DFFE_NP1N_ $_DFFE_NN0P_ $_DFFE_NN0N_ $_DFFE_NN1P_ $_DFFE_NN1N_" *) +(* techmap_celltype = "$_DFFE_[PN][PN][01][PN]_" *) module \$_DFFE_xxxx_ (input D, C, R, E, output Q); parameter _TECHMAP_CELLTYPE_ = ""; @@ -17,7 +17,7 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q); endmodule -(* techmap_celltype = "$_SDFFE_PP0P_ $_SDFFE_PP0N_ $_SDFFE_PP1P_ $_SDFFE_PP1N_ $_SDFFE_PN0P_ $_SDFFE_PN0N_ $_SDFFE_PN1P_ $_SDFFE_PN1N_ $_SDFFE_NP0P_ $_SDFFE_NP0N_ $_SDFFE_NP1P_ $_SDFFE_NP1N_ $_SDFFE_NN0P_ $_SDFFE_NN0N_ $_SDFFE_NN1P_ $_SDFFE_NN1N_" *) +(* techmap_celltype = "$_SDFFE_[PN][PN][01][PN]_" *) module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); parameter _TECHMAP_CELLTYPE_ = ""; @@ -36,7 +36,7 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); endmodule -(* techmap_celltype = "$_SDFFCE_PP0P_ $_SDFFCE_PP0N_ $_SDFFCE_PP1P_ $_SDFFCE_PP1N_ $_SDFFCE_PN0P_ $_SDFFCE_PN0N_ $_SDFFCE_PN1P_ $_SDFFCE_PN1N_ $_SDFFCE_NP0P_ $_SDFFCE_NP0N_ $_SDFFCE_NP1P_ $_SDFFCE_NP1N_ $_SDFFCE_NN0P_ $_SDFFCE_NN0N_ $_SDFFCE_NN1P_ $_SDFFCE_NN1N_" *) +(* techmap_celltype = "$_SDFFCE_[PN][PN][01][PN]_" *) module \$_SDFFCE_xxxx_ (input D, C, R, E, output Q); parameter _TECHMAP_CELLTYPE_ = ""; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index d7b11d431..4d1e968ae 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -219,11 +219,11 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_ffs")) { - run("dff2dffs -match-init"); run("opt_clean"); - if (!nodffe) - run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*"); - run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r"); + if (nodffe) + run("dfflegalize -cell $_DFF_?_ 0 -cell $_SDFF_?P?_ r -cell $_DFF_?P?_ r"); + else + run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index ae6d3539c..b945889fe 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -292,11 +292,9 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); run("check"); - run("opt"); + run("opt -nodffe -nosdff"); run("fsm"); run("opt"); - run("opt_dff"); - run("opt"); run("wreduce"); run("peepopt"); run("opt_clean"); diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index fef6aab77..b06cf5b72 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -8,7 +8,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v)) # Add the cell models and mappings for the VQM backend -families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive +families := max10 cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v deleted file mode 100644 index 6a52a0f95..000000000 --- a/techlibs/intel/arria10gx/cells_arith.v +++ /dev/null @@ -1,71 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// NOTE: This is still WIP. -(* techmap_celltype = "$alu" *) -module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - (* force_downto *) - input [A_WIDTH-1:0] A; - (* force_downto *) - input [B_WIDTH-1:0] B; - (* force_downto *) - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - //output [Y_WIDTH-1:0] CO; - output CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - (* force_downto *) - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - (* force_downto *) - wire [Y_WIDTH-1:0] AA = A_buf; - (* force_downto *) - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - //wire [Y_WIDTH:0] C = {CO, CI}; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; - - /* Start implementation */ - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - - genvar i; - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); - assign CO = COx[Y_WIDTH]; - end - else - fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); - end: slice - endgenerate - /* End implementation */ - assign X = AA ^ BB; - -endmodule diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v deleted file mode 100644 index 83f5881da..000000000 --- a/techlibs/intel/arria10gx/cells_map.v +++ /dev/null @@ -1,54 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -// Input buffer map -module \$__inpad (input I, output O); - twentynm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); -endmodule - -// Output buffer map -module \$__outpad (input I, output O); - twentynm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); -endmodule - -// LUT Map -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - (* force_downto *) - input [WIDTH-1:0] A; - output Y; - generate - if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end else - if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); - end /*else - if(WIDTH == 3) begin - fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1)); - end else - if(WIDTH == 4) begin - fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3])); - end*/ else - wire _TECHMAP_FAIL_ = 1; - endgenerate -endmodule // - - diff --git a/techlibs/intel/arria10gx/cells_sim.v b/techlibs/intel/arria10gx/cells_sim.v deleted file mode 100644 index e892b377e..000000000 --- a/techlibs/intel/arria10gx/cells_sim.v +++ /dev/null @@ -1,59 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -module VCC (output V); - assign V = 1'b1; -endmodule // VCC - -module GND (output G); - assign G = 1'b0; -endmodule // GND - -/* Altera Arria 10 GX devices Input Buffer Primitive */ -module twentynm_io_ibuf (output o, input i, input ibar); - assign ibar = ibar; - assign o = i; -endmodule // twentynm_io_ibuf - -/* Altera Arria 10 GX devices Output Buffer Primitive */ -module twentynm_io_obuf (output o, input i, input oe); - assign o = i; - assign oe = oe; -endmodule // twentynm_io_obuf - -/* Altera Arria 10 GX LUT Primitive */ -module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, - input datae, dataf, datag, cin, - input sharein); - -parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; -parameter dont_touch = "off"; -parameter lpm_type = "twentynm_lcell_comb"; -parameter shared_arith = "off"; -parameter extended_lut = "off"; - -// TODO: This is still WIP -initial begin - $display("Simulation model is still under investigation\n"); -end - -endmodule // twentynm_lcell_comb - - - diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v deleted file mode 100644 index 6a52a0f95..000000000 --- a/techlibs/intel/cyclonev/cells_arith.v +++ /dev/null @@ -1,71 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -// NOTE: This is still WIP. -(* techmap_celltype = "$alu" *) -module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - (* force_downto *) - input [A_WIDTH-1:0] A; - (* force_downto *) - input [B_WIDTH-1:0] B; - (* force_downto *) - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - //output [Y_WIDTH-1:0] CO; - output CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; - - (* force_downto *) - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - (* force_downto *) - wire [Y_WIDTH-1:0] AA = A_buf; - (* force_downto *) - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - //wire [Y_WIDTH:0] C = {CO, CI}; - wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; - - /* Start implementation */ - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - - genvar i; - generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); - assign CO = COx[Y_WIDTH]; - end - else - fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); - end: slice - endgenerate - /* End implementation */ - assign X = AA ^ BB; - -endmodule diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v deleted file mode 100644 index 0041481ab..000000000 --- a/techlibs/intel/cyclonev/cells_map.v +++ /dev/null @@ -1,126 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -// > c60k28 (Viacheslav, VT) [at] yandex [dot] com -// > Intel FPGA technology mapping. User must first simulate the generated \ -// > netlist before going to test it on board. - -// Input buffer map -module \$__inpad (input I, output O); - cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); -endmodule - -// Output buffer map -module \$__outpad (input I, output O); - cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); -endmodule - -// LUT Map -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - (* force_downto *) - input [WIDTH-1:0] A; - output Y; - wire VCC; - wire GND; - assign {VCC,GND} = {1'b1,1'b0}; - - generate - if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end - else - if (WIDTH == 2) begin - cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(VCC), - .datad(VCC), - .datae(VCC), - .dataf(VCC), - .datag(VCC)); - end - else - if(WIDTH == 3) begin - cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(VCC), - .datae(VCC), - .dataf(VCC), - .datag(VCC)); - end - else - if(WIDTH == 4) begin - cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3]), - .datae(VCC), - .dataf(VCC), - .datag(VCC)); - end - else - if(WIDTH == 5) begin - cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(VCC), - .datag(VCC)); - end - else - if(WIDTH == 6) begin - cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), - .datag(VCC)); - end - /*else - if(WIDTH == 7) begin - TODO: There's not a just 7-input function on Cyclone V, see the following note: - **Extended LUT Mode** - Use extended LUT mode to implement a specific set of 7-input functions. The set must - be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. - [source](Device Interfaces and Integration Basics for Cyclone V Devices). - end*/ - else - wire _TECHMAP_FAIL_ = 1; - endgenerate -endmodule // lut - - diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 1fa98d098..a513528f7 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,11 +36,11 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); - log(" Cyclone V and Arria 10 GX devices are experimental.\n"); + log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); @@ -147,9 +147,11 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + + if (family_opt == "cyclonev") + log_cmd_error("Cyclone V synthesis has been moved to synth_intel_alm.\n"); + if (family_opt != "max10" && - family_opt != "arria10gx" && - family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && family_opt != "cyclone10lp") @@ -202,8 +204,6 @@ struct SynthIntelPass : public ScriptPass { run("opt -fast -mux_undef -undriven -fine -full"); run("memory_map"); run("opt -undriven -fine"); - run("dff2dffe -direct-match $_DFF_*"); - run("opt -fine"); run("techmap -map +/techmap.v"); run("opt -full"); run("clean -purge"); @@ -218,10 +218,7 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - if (family_opt == "arria10gx" || family_opt == "cyclonev") - run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); - else - run("abc -lut 4" + string(retime ? " -dff" : "")); + run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); } diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc index e36c81c0e..da88762c4 100644 --- a/techlibs/intel_alm/Makefile.inc +++ b/techlibs/intel_alm/Makefile.inc @@ -14,6 +14,8 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v)) $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v)) +$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v)) + # RAM $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt)) $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt)) diff --git a/techlibs/intel_alm/common/dsp_map.v b/techlibs/intel_alm/common/dsp_map.v index d1bc25e65..e12e777a4 100644 --- a/techlibs/intel_alm/common/dsp_map.v +++ b/techlibs/intel_alm/common/dsp_map.v @@ -1,3 +1,5 @@ +`default_nettype none + module __MUL27X27(A, B, Y); parameter A_SIGNED = 1; diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index 7e72dab0d..bdb6d18d5 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,5 +1,8 @@ (* abc9_box *) -module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y); +module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y); + +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify @@ -7,32 +10,74 @@ specify (B *> Y) = 3928; endspecify -assign Y = $signed(A) * $signed(B); +wire [53:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 3180; (B *> Y) = 3982; endspecify -assign Y = $signed(A) * $signed(B); +wire [35:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 2818; (B *> Y) = 3051; endspecify -assign Y = $signed(A) * $signed(B); +wire [17:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v index 820b0430e..874f293b1 100644 --- a/techlibs/intel_alm/common/megafunction_bb.v +++ b/techlibs/intel_alm/common/megafunction_bb.v @@ -2,6 +2,306 @@ `default_nettype none (* blackbox *) +module altera_pll +#( + parameter reference_clock_frequency = "0 ps", + parameter fractional_vco_multiplier = "false", + parameter pll_type = "General", + parameter pll_subtype = "General", + parameter number_of_clocks = 1, + parameter operation_mode = "internal feedback", + parameter deserialization_factor = 4, + parameter data_rate = 0, + + parameter sim_additional_refclk_cycles_to_lock = 0, + parameter output_clock_frequency0 = "0 ps", + parameter phase_shift0 = "0 ps", + parameter duty_cycle0 = 50, + + parameter output_clock_frequency1 = "0 ps", + parameter phase_shift1 = "0 ps", + parameter duty_cycle1 = 50, + + parameter output_clock_frequency2 = "0 ps", + parameter phase_shift2 = "0 ps", + parameter duty_cycle2 = 50, + + parameter output_clock_frequency3 = "0 ps", + parameter phase_shift3 = "0 ps", + parameter duty_cycle3 = 50, + + parameter output_clock_frequency4 = "0 ps", + parameter phase_shift4 = "0 ps", + parameter duty_cycle4 = 50, + + parameter output_clock_frequency5 = "0 ps", + parameter phase_shift5 = "0 ps", + parameter duty_cycle5 = 50, + + parameter output_clock_frequency6 = "0 ps", + parameter phase_shift6 = "0 ps", + parameter duty_cycle6 = 50, + + parameter output_clock_frequency7 = "0 ps", + parameter phase_shift7 = "0 ps", + parameter duty_cycle7 = 50, + + parameter output_clock_frequency8 = "0 ps", + parameter phase_shift8 = "0 ps", + parameter duty_cycle8 = 50, + + parameter output_clock_frequency9 = "0 ps", + parameter phase_shift9 = "0 ps", + parameter duty_cycle9 = 50, + + + parameter output_clock_frequency10 = "0 ps", + parameter phase_shift10 = "0 ps", + parameter duty_cycle10 = 50, + + parameter output_clock_frequency11 = "0 ps", + parameter phase_shift11 = "0 ps", + parameter duty_cycle11 = 50, + + parameter output_clock_frequency12 = "0 ps", + parameter phase_shift12 = "0 ps", + parameter duty_cycle12 = 50, + + parameter output_clock_frequency13 = "0 ps", + parameter phase_shift13 = "0 ps", + parameter duty_cycle13 = 50, + + parameter output_clock_frequency14 = "0 ps", + parameter phase_shift14 = "0 ps", + parameter duty_cycle14 = 50, + + parameter output_clock_frequency15 = "0 ps", + parameter phase_shift15 = "0 ps", + parameter duty_cycle15 = 50, + + parameter output_clock_frequency16 = "0 ps", + parameter phase_shift16 = "0 ps", + parameter duty_cycle16 = 50, + + parameter output_clock_frequency17 = "0 ps", + parameter phase_shift17 = "0 ps", + parameter duty_cycle17 = 50, + + parameter clock_name_0 = "", + parameter clock_name_1 = "", + parameter clock_name_2 = "", + parameter clock_name_3 = "", + parameter clock_name_4 = "", + parameter clock_name_5 = "", + parameter clock_name_6 = "", + parameter clock_name_7 = "", + parameter clock_name_8 = "", + + parameter clock_name_global_0 = "false", + parameter clock_name_global_1 = "false", + parameter clock_name_global_2 = "false", + parameter clock_name_global_3 = "false", + parameter clock_name_global_4 = "false", + parameter clock_name_global_5 = "false", + parameter clock_name_global_6 = "false", + parameter clock_name_global_7 = "false", + parameter clock_name_global_8 = "false", + + parameter m_cnt_hi_div = 1, + parameter m_cnt_lo_div = 1, + parameter m_cnt_bypass_en = "false", + parameter m_cnt_odd_div_duty_en = "false", + parameter n_cnt_hi_div = 1, + parameter n_cnt_lo_div = 1, + parameter n_cnt_bypass_en = "false", + parameter n_cnt_odd_div_duty_en = "false", + parameter c_cnt_hi_div0 = 1, + parameter c_cnt_lo_div0 = 1, + parameter c_cnt_bypass_en0 = "false", + parameter c_cnt_in_src0 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en0 = "false", + parameter c_cnt_prst0 = 1, + parameter c_cnt_ph_mux_prst0 = 0, + parameter c_cnt_hi_div1 = 1, + parameter c_cnt_lo_div1 = 1, + parameter c_cnt_bypass_en1 = "false", + parameter c_cnt_in_src1 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en1 = "false", + parameter c_cnt_prst1 = 1, + parameter c_cnt_ph_mux_prst1 = 0, + parameter c_cnt_hi_div2 = 1, + parameter c_cnt_lo_div2 = 1, + parameter c_cnt_bypass_en2 = "false", + parameter c_cnt_in_src2 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en2 = "false", + parameter c_cnt_prst2 = 1, + parameter c_cnt_ph_mux_prst2 = 0, + parameter c_cnt_hi_div3 = 1, + parameter c_cnt_lo_div3 = 1, + parameter c_cnt_bypass_en3 = "false", + parameter c_cnt_in_src3 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en3 = "false", + parameter c_cnt_prst3 = 1, + parameter c_cnt_ph_mux_prst3 = 0, + parameter c_cnt_hi_div4 = 1, + parameter c_cnt_lo_div4 = 1, + parameter c_cnt_bypass_en4 = "false", + parameter c_cnt_in_src4 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en4 = "false", + parameter c_cnt_prst4 = 1, + parameter c_cnt_ph_mux_prst4 = 0, + parameter c_cnt_hi_div5 = 1, + parameter c_cnt_lo_div5 = 1, + parameter c_cnt_bypass_en5 = "false", + parameter c_cnt_in_src5 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en5 = "false", + parameter c_cnt_prst5 = 1, + parameter c_cnt_ph_mux_prst5 = 0, + parameter c_cnt_hi_div6 = 1, + parameter c_cnt_lo_div6 = 1, + parameter c_cnt_bypass_en6 = "false", + parameter c_cnt_in_src6 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en6 = "false", + parameter c_cnt_prst6 = 1, + parameter c_cnt_ph_mux_prst6 = 0, + parameter c_cnt_hi_div7 = 1, + parameter c_cnt_lo_div7 = 1, + parameter c_cnt_bypass_en7 = "false", + parameter c_cnt_in_src7 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en7 = "false", + parameter c_cnt_prst7 = 1, + parameter c_cnt_ph_mux_prst7 = 0, + parameter c_cnt_hi_div8 = 1, + parameter c_cnt_lo_div8 = 1, + parameter c_cnt_bypass_en8 = "false", + parameter c_cnt_in_src8 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en8 = "false", + parameter c_cnt_prst8 = 1, + parameter c_cnt_ph_mux_prst8 = 0, + parameter c_cnt_hi_div9 = 1, + parameter c_cnt_lo_div9 = 1, + parameter c_cnt_bypass_en9 = "false", + parameter c_cnt_in_src9 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en9 = "false", + parameter c_cnt_prst9 = 1, + parameter c_cnt_ph_mux_prst9 = 0, + parameter c_cnt_hi_div10 = 1, + parameter c_cnt_lo_div10 = 1, + parameter c_cnt_bypass_en10 = "false", + parameter c_cnt_in_src10 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en10 = "false", + parameter c_cnt_prst10 = 1, + parameter c_cnt_ph_mux_prst10 = 0, + parameter c_cnt_hi_div11 = 1, + parameter c_cnt_lo_div11 = 1, + parameter c_cnt_bypass_en11 = "false", + parameter c_cnt_in_src11 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en11 = "false", + parameter c_cnt_prst11 = 1, + parameter c_cnt_ph_mux_prst11 = 0, + parameter c_cnt_hi_div12 = 1, + parameter c_cnt_lo_div12 = 1, + parameter c_cnt_bypass_en12 = "false", + parameter c_cnt_in_src12 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en12 = "false", + parameter c_cnt_prst12 = 1, + parameter c_cnt_ph_mux_prst12 = 0, + parameter c_cnt_hi_div13 = 1, + parameter c_cnt_lo_div13 = 1, + parameter c_cnt_bypass_en13 = "false", + parameter c_cnt_in_src13 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en13 = "false", + parameter c_cnt_prst13 = 1, + parameter c_cnt_ph_mux_prst13 = 0, + parameter c_cnt_hi_div14 = 1, + parameter c_cnt_lo_div14 = 1, + parameter c_cnt_bypass_en14 = "false", + parameter c_cnt_in_src14 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en14 = "false", + parameter c_cnt_prst14 = 1, + parameter c_cnt_ph_mux_prst14 = 0, + parameter c_cnt_hi_div15 = 1, + parameter c_cnt_lo_div15 = 1, + parameter c_cnt_bypass_en15 = "false", + parameter c_cnt_in_src15 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en15 = "false", + parameter c_cnt_prst15 = 1, + parameter c_cnt_ph_mux_prst15 = 0, + parameter c_cnt_hi_div16 = 1, + parameter c_cnt_lo_div16 = 1, + parameter c_cnt_bypass_en16 = "false", + parameter c_cnt_in_src16 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en16 = "false", + parameter c_cnt_prst16 = 1, + parameter c_cnt_ph_mux_prst16 = 0, + parameter c_cnt_hi_div17 = 1, + parameter c_cnt_lo_div17 = 1, + parameter c_cnt_bypass_en17 = "false", + parameter c_cnt_in_src17 = "ph_mux_clk", + parameter c_cnt_odd_div_duty_en17 = "false", + parameter c_cnt_prst17 = 1, + parameter c_cnt_ph_mux_prst17 = 0, + parameter pll_vco_div = 1, + parameter pll_slf_rst = "false", + parameter pll_bw_sel = "low", + parameter pll_output_clk_frequency = "0 MHz", + parameter pll_cp_current = 0, + parameter pll_bwctrl = 0, + parameter pll_fractional_division = 1, + parameter pll_fractional_cout = 24, + parameter pll_dsm_out_sel = "1st_order", + parameter mimic_fbclk_type = "gclk", + parameter pll_fbclk_mux_1 = "glb", + parameter pll_fbclk_mux_2 = "fb_1", + parameter pll_m_cnt_in_src = "ph_mux_clk", + parameter pll_vcoph_div = 1, + parameter refclk1_frequency = "0 MHz", + parameter pll_clkin_0_src = "clk_0", + parameter pll_clkin_1_src = "clk_0", + parameter pll_clk_loss_sw_en = "false", + parameter pll_auto_clk_sw_en = "false", + parameter pll_manu_clk_sw_en = "false", + parameter pll_clk_sw_dly = 0, + parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", + parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss" +) ( + //input + input refclk, + input refclk1, + input fbclk, + input rst, + input phase_en, + input updn, + input [2:0] num_phase_shifts, + input scanclk, + input [4:0] cntsel, + input [63:0] reconfig_to_pll, + input extswitch, + input adjpllin, + input cclk, + + //output + output [ number_of_clocks -1 : 0] outclk, + output fboutclk, + output locked, + output phase_done, + output [63:0] reconfig_from_pll, + output activeclk, + output [1:0] clkbad, + output [7:0] phout, + output [1:0] lvds_clk, + output [1:0] loaden, + output [1:0] extclk_out, + output [ number_of_clocks -1 : 0] cascade_out, + + //inout + inout zdbfbclk +); + +endmodule + + +(* blackbox *) module altera_std_synchronizer(clk, din, dout, reset_n); parameter depth = 2; @@ -14,6 +314,137 @@ output dout; endmodule (* blackbox *) +module altddio_in ( + datain, // required port, DDR input data + inclock, // required port, input reference clock to sample data by + inclocken, // enable data clock + aset, // asynchronous set + aclr, // asynchronous clear + sset, // synchronous set + sclr, // synchronous clear + dataout_h, // data sampled at the rising edge of inclock + dataout_l // data sampled at the falling edge of inclock +); + +parameter width = 1; +parameter power_up_high = "OFF"; +parameter invert_input_clocks = "OFF"; +parameter intended_device_family = "Stratix"; +parameter lpm_type = "altddio_in"; +parameter lpm_hint = "UNUSED"; + +input [width-1:0] datain; +input inclock; +input inclocken; +input aset; +input aclr; +input sset; +input sclr; + +output [width-1:0] dataout_h; +output [width-1:0] dataout_l; + +endmodule + + +(* blackbox *) +module altddio_out ( + datain_h, + datain_l, + outclock, + outclocken, + aset, + aclr, + sset, + sclr, + oe, + dataout, + oe_out +); + +parameter width = 1; +parameter power_up_high = "OFF"; +parameter oe_reg = "UNUSED"; +parameter extend_oe_disable = "UNUSED"; +parameter intended_device_family = "Stratix"; +parameter invert_output = "OFF"; +parameter lpm_type = "altddio_out"; +parameter lpm_hint = "UNUSED"; + +input [width-1:0] datain_h; +input [width-1:0] datain_l; +input outclock; +input outclocken; +input aset; +input aclr; +input sset; +input sclr; +input oe; + +output [width-1:0] dataout; +output [width-1:0] oe_out; + +endmodule + + +(* blackbox *) +module altddio_bidir ( + datain_h, + datain_l, + inclock, + inclocken, + outclock, + outclocken, + aset, + aclr, + sset, + sclr, + oe, + dataout_h, + dataout_l, + combout, + oe_out, + dqsundelayedout, + padio +); + +// GLOBAL PARAMETER DECLARATION +parameter width = 1; // required parameter +parameter power_up_high = "OFF"; +parameter oe_reg = "UNUSED"; +parameter extend_oe_disable = "UNUSED"; +parameter implement_input_in_lcell = "UNUSED"; +parameter invert_output = "OFF"; +parameter intended_device_family = "Stratix"; +parameter lpm_type = "altddio_bidir"; +parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION +input [width-1:0] datain_h; +input [width-1:0] datain_l; +input inclock; +input inclocken; +input outclock; +input outclocken; +input aset; +input aclr; +input sset; +input sclr; +input oe; + +// OUTPUT PORT DECLARATION +output [width-1:0] dataout_h; +output [width-1:0] dataout_l; +output [width-1:0] combout; +output [width-1:0] oe_out; +output [width-1:0] dqsundelayedout; +// BIDIRECTIONAL PORT DECLARATION +inout [width-1:0] padio; + +endmodule + + +(* blackbox *) module altiobuf_in(datain, dataout); parameter enable_bus_hold = "FALSE"; @@ -134,7 +565,9 @@ endmodule module cyclonev_mac(ax, ay, resulta); parameter ax_width = 9; +parameter signed_max = "true"; parameter ay_scan_in_width = 9; +parameter signed_may = "true"; parameter result_a_width = 18; parameter operation_mode = "M9x9"; @@ -148,7 +581,9 @@ endmodule module cyclone10gx_mac(ax, ay, resulta); parameter ax_width = 18; +parameter signed_max = "true"; parameter ay_scan_in_width = 18; +parameter signed_may = "true"; parameter result_a_width = 36; parameter operation_mode = "M18X18_FULL"; diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 9bc532ca2..3b4628675 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -174,20 +174,62 @@ endmodule module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y); -`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(27), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(27), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(54), + .operation_mode("M27x27") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y); -`MAC #(.ax_width(18), .ay_scan_in_width(18), .result_a_width(36), .operation_mode("M18x18_FULL")) _TECHMAP_REPLACE_ (.ax(B), .ay(A), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(18), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(18), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(36), + .operation_mode("M18x18_FULL") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y); -`MAC #(.ax_width(9), .ay_scan_in_width(9), .result_a_width(18), .operation_mode("M9x9")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(9), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(9), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(18), + .operation_mode("M9x9") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel_alm/cyclonev/cells_sim.v index 9b2a10e72..9b2a10e72 100644 --- a/techlibs/intel/cyclonev/cells_sim.v +++ b/techlibs/intel_alm/cyclonev/cells_sim.v diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 9da91361a..6719eb65c 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -178,7 +178,7 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("begin")) { if (family_opt == "cyclonev") - run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); + run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str())); @@ -200,6 +200,8 @@ struct SynthIntelALMPass : public ScriptPass { run("opt_expr"); run("opt_clean"); run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); run("opt"); run("wreduce"); run("peepopt"); @@ -212,23 +214,25 @@ struct SynthIntelALMPass : public ScriptPass { run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)"); } else if (!nodsp) { // Cyclone V supports 9x9 multiplication, Cyclone 10 GX does not. - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=19 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL27X27"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL27X27"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=19 -D DSP_NAME=__MUL27X27"); run("chtype -set $mul t:$__soft_mul"); if (family_opt == "cyclonev") { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18"); run("chtype -set $mul t:$__soft_mul"); - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL9X9"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9"); run("chtype -set $mul t:$__soft_mul"); } else if (family_opt == "cyclone10gx") { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18"); run("chtype -set $mul t:$__soft_mul"); } } run("alumacc"); run("techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v"); run("opt"); - run("fsm"); - run("opt -fast"); run("memory -nomap"); run("opt_clean"); } @@ -250,7 +254,6 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("map_ffs")) { run("techmap"); - run("dff2dffe"); run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0"); run("techmap -map +/intel_alm/common/dff_map.v"); run("opt -full -undriven -mux_undef"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 970196de9..0adec57a2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -357,11 +357,9 @@ struct SynthXilinxPass : public ScriptPass run("opt_expr"); run("opt_clean"); run("check"); - run("opt"); + run("opt -nodffe -nosdff"); run("fsm"); run("opt"); - run("opt_dff"); - run("opt"); if (help_mode) run("wreduce [-keepdc]", "(option for '-widemux')"); else diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index b76bdb653..54b4a279b 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1,3 +1,3 @@ /*_ref.v -/*.aag.log -/*.aig.log +/*.log +/neg.out/ diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys index d3281ab89..deb90e051 100644 --- a/tests/arch/anlogic/dffs.ys +++ b/tests/arch/anlogic/dffs.ys @@ -15,6 +15,5 @@ proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index 437a91cfc..baed64fcd 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,9 +1,10 @@ module top +#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12) ( - input [5:0] x, - input [5:0] y, + input [X_WIDTH-1:0] x, + input [Y_WIDTH-1:0] y, - output [11:0] A, + output [A_WIDTH-1:0] A, ); assign A = x * y; endmodule diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index ba91e5fc0..a77986bbc 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -10,8 +10,8 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:L6MUX21 -select -assert-count 15 t:LUT4 -select -assert-count 6 t:PFUMX +select -assert-max 1 t:L6MUX21 +select -assert-max 16 t:LUT4 +select -assert-max 7 t:PFUMX select -assert-count 6 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys index 49dc7f256..86d446439 100644 --- a/tests/arch/efinix/adffs.ys +++ b/tests/arch/efinix/adffs.ys @@ -32,9 +32,8 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read @@ -45,6 +44,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys index af787ab67..f9111873c 100644 --- a/tests/arch/efinix/dffs.ys +++ b/tests/arch/efinix/dffs.ys @@ -19,6 +19,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys index 88e88c15a..fba7c2fa5 100644 --- a/tests/arch/gowin/init.ys +++ b/tests/arch/gowin/init.ys @@ -45,24 +45,25 @@ flatten synth_gowin -run coarse: # check the flops mapped as expected -select -assert-count 1 t:DFF +select -assert-count 2 t:DFF select -assert-count 1 t:DFFC select -assert-count 1 t:DFFCE -select -assert-count 1 t:DFFE -select -assert-count 1 t:DFFN +select -assert-count 0 t:DFFE +select -assert-count 2 t:DFFN select -assert-count 1 t:DFFNC select -assert-count 1 t:DFFNCE -select -assert-count 1 t:DFFNE +select -assert-count 0 t:DFFNE select -assert-count 1 t:DFFNP select -assert-count 1 t:DFFNPE select -assert-count 0 t:DFFNR select -assert-count 0 t:DFFNRE -select -assert-count 2 t:DFFNS -select -assert-count 2 t:DFFNSE +select -assert-count 3 t:DFFNS +select -assert-count 1 t:DFFNSE select -assert-count 1 t:DFFP select -assert-count 1 t:DFFPE select -assert-count 0 t:DFFR select -assert-count 0 t:DFFRE -select -assert-count 2 t:DFFS -select -assert-count 2 t:DFFSE -select -assert-count 12 t:LUT2 +select -assert-count 3 t:DFFS +select -assert-count 1 t:DFFSE +select -assert-count 4 t:LUT2 +select -assert-count 4 t:LUT4 diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys index 04fa2ad24..4565dcc64 100644 --- a/tests/arch/intel_alm/adffs.ys +++ b/tests/arch/intel_alm/adffs.ys @@ -77,10 +77,9 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF -select -assert-count 1 t:MISTRAL_NOT -select -assert-count 1 t:MISTRAL_ALUT2 +select -assert-count 2 t:MISTRAL_NOT -select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 %% t:* %D +select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D design -load read @@ -90,7 +89,6 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF -select -assert-count 1 t:MISTRAL_NOT -select -assert-count 1 t:MISTRAL_ALUT2 +select -assert-count 2 t:MISTRAL_NOT -select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 %% t:* %D +select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys index 6491b2e08..e54b5c21e 100644 --- a/tests/arch/intel_alm/fsm.ys +++ b/tests/arch/intel_alm/fsm.ys @@ -12,12 +12,13 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:MISTRAL_FF +select -assert-max 1 t:MISTRAL_NOT select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1 -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-max 1 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1 +select -assert-max 1 t:MISTRAL_ALUT3 +select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2 -select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -reset read_verilog ../common/fsm.v @@ -34,9 +35,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:MISTRAL_FF +select -assert-max 1 t:MISTRAL_NOT select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1 select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1 -select -assert-max 1 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1 +select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1 select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4 select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2 -select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys index 92f00156a..49934740f 100644 --- a/tests/arch/intel_alm/mul.ys +++ b/tests/arch/intel_alm/mul.ys @@ -1,23 +1,60 @@ read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat - select -assert-count 1 t:MISTRAL_MUL9X9 select -assert-none t:MISTRAL_MUL9X9 %% t:* %D +# Cyclone 10 GX does not have 9x9 multipliers. + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL18X18 +select -assert-none t:MISTRAL_MUL18X18 %% t:* %D + design -reset read_verilog ../common/mul.v +chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18. select -assert-count 1 t:MISTRAL_MUL18X18 select -assert-none t:MISTRAL_MUL18X18 %% t:* %D + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL27X27 +select -assert-none t:MISTRAL_MUL27X27 %% t:* %D + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL27X27 +select -assert-none t:MISTRAL_MUL27X27 %% t:* %D diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index 01cc78e1b..ac3b9b08f 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -70,8 +70,9 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 5 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D +select -assert-max 2 t:MISTRAL_ALUT5 +select -assert-max 5 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read diff --git a/tests/opt/bug2318.ys b/tests/opt/bug2318.ys new file mode 100644 index 000000000..9de6f88ec --- /dev/null +++ b/tests/opt/bug2318.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module t(input [3:0] A, input [3:0] B, output signed [3:0] Y); + +wire [7:0] P = A * B; +wire signed [7:0] SP = P; +wire signed [3:0] SB = B; +assign Y = SP / SB; + +endmodule +EOT + +equiv_opt -assert peepopt diff --git a/tests/opt/opt_dff_dffmux.ys b/tests/opt/opt_dff_dffmux.ys new file mode 100644 index 000000000..43190cc31 --- /dev/null +++ b/tests/opt/opt_dff_dffmux.ys @@ -0,0 +1,129 @@ +design -reset +read_verilog <<EOT +module opt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +select -assert-count 1 t:$dffe r:WIDTH=2 %i +select -assert-count 0 t:$dffe %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +wreduce +select -assert-count 1 t:$dffe r:WIDTH=2 %i +select -assert-count 0 t:$dffe %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +select -assert-count 1 t:$dffe r:WIDTH=2 %i +select -assert-count 0 t:$dffe %% t:* %D + +################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o); + always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +select -assert-count 1 t:$dffe r:WIDTH=4 %i +select -assert-count 0 t:$dffe %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +wreduce +select -assert-count 1 t:$sdffe r:WIDTH=2 %i +select -assert-count 0 t:$sdffe %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +equiv_opt -assert opt +design -load postopt +wreduce +select -assert-count 1 t:$sdffe r:WIDTH=2 %i +select -assert-count 0 t:$sdffe %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module opt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + initial o <= 4'b0010; + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +# NB: equiv_opt uses equiv_induct which covers +# only the induction half of temporal induction +# --- missing the base-case half +# This makes it akin to `sat -tempinduct-inductonly` +# instead of `sat -tempinduct-baseonly` or +# `sat -tempinduct` which is necessary for this +# testcase +#equiv_opt -assert opt + +design -save gold +opt +wreduce +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -tempinduct -verify -prove-asserts -show-ports miter + +design -load gate +select -assert-count 1 t:$sdffe r:WIDTH=3 %i +select -assert-count 0 t:$sdffe %% t:* %D diff --git a/tests/opt/opt_share_bug2334.ys b/tests/opt/opt_share_bug2334.ys new file mode 100644 index 000000000..004d98349 --- /dev/null +++ b/tests/opt/opt_share_bug2334.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y); + +wire [3:0] t = A + C; + +assign Y = S ? A + B : {4{t[0]}}; + +endmodule + +EOT + +equiv_opt -assert opt_share diff --git a/tests/opt/opt_share_bug2335.ys b/tests/opt/opt_share_bug2335.ys new file mode 100644 index 000000000..0846a9ec3 --- /dev/null +++ b/tests/opt/opt_share_bug2335.ys @@ -0,0 +1,27 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A, B, C; +input S; +input [1:0] T; +output [3:0] X; +output reg [3:0] Y; + +wire [3:0] D = A + B; + +assign X = S ? D : A + C; +always @* begin + case(T) + 2'b01: Y <= A; + 2'b10: Y <= B; + default: Y <= D; + endcase +end + +endmodule + +EOT + +proc +equiv_opt -assert opt_share diff --git a/tests/opt/opt_share_bug2336.ys b/tests/opt/opt_share_bug2336.ys new file mode 100644 index 000000000..cd472ef46 --- /dev/null +++ b/tests/opt/opt_share_bug2336.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT + +module top(input [3:0] A, B, C, input S, output [2:0] O); + +wire [3:0] tb = A + B; +wire [3:0] tc = A + C; + +assign O = S ? tb[3:1] : tc[3:1]; + +endmodule + +EOT + +equiv_opt -assert opt_share diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v new file mode 100644 index 000000000..8166688e6 --- /dev/null +++ b/tests/simple/const_branch_finish.v @@ -0,0 +1,39 @@ +`define CONSTANT_CHECK \ + if (WIDTH === 'bx) begin \ + $display("FAIL"); \ + $finish; \ + end + +module top; + parameter WIDTH = 32; + integer j; + initial begin + `CONSTANT_CHECK + if (WIDTH == 32) begin : procedural_conditional_block + `CONSTANT_CHECK + end + case (WIDTH) + 32: `CONSTANT_CHECK + default: ; + endcase + for (j = 0; j < 2; j = j + 1) begin : procedural_loop_block + `CONSTANT_CHECK + end + end + generate + begin : unconditional_block + initial `CONSTANT_CHECK + end + if (WIDTH == 32) begin : conditional_block + initial `CONSTANT_CHECK + end + case (WIDTH) + 32: initial `CONSTANT_CHECK + default: ; + endcase + genvar i; + for (i = 0; i < 2; i = i + 1) begin : loop_block + initial `CONSTANT_CHECK + end + endgenerate +endmodule diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 0e353ad9b..12327b36e 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -159,3 +159,104 @@ generate end endgenerate endmodule + +// ------------------------------------------ + +module gen_test7; + reg [2:0] out1; + reg [2:0] out2; + wire [2:0] out3; + generate + begin : cond + reg [2:0] sub_out1; + reg [2:0] sub_out2; + wire [2:0] sub_out3; + initial begin : init + reg signed [31:0] x; + x = 2 ** 2; + out1 = x; + sub_out1 = x; + end + always @* begin : proc + reg signed [31:0] x; + x = 2 ** 1; + out2 = x; + sub_out2 = x; + end + genvar x; + for (x = 0; x < 3; x = x + 1) begin + assign out3[x] = 1; + assign sub_out3[x] = 1; + end + end + endgenerate + +// `define VERIFY +`ifdef VERIFY + assert property (out1 == 4); + assert property (out2 == 2); + assert property (out3 == 7); + assert property (cond.sub_out1 == 4); + assert property (cond.sub_out2 == 2); + assert property (cond.sub_out3 == 7); +`endif +endmodule + +// ------------------------------------------ + +module gen_test8; + +// `define VERIFY +`ifdef VERIFY + `define ASSERT(expr) assert property (expr); +`else + `define ASSERT(expr) +`endif + + wire [1:0] x = 2'b11; + generate + begin : A + wire [1:0] x; + begin : B + wire [1:0] x = 2'b00; + `ASSERT(x == 0) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + `ASSERT(gen_test8.x == 3) + `ASSERT(gen_test8.A.x == 2) + `ASSERT(gen_test8.A.C.x == 1) + `ASSERT(gen_test8.A.B.x == 0) + end + begin : C + wire [1:0] x = 2'b01; + `ASSERT(x == 1) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + `ASSERT(gen_test8.x == 3) + `ASSERT(gen_test8.A.x == 2) + `ASSERT(gen_test8.A.C.x == 1) + `ASSERT(gen_test8.A.B.x == 0) + end + assign x = B.x ^ 2'b11 ^ C.x; + `ASSERT(x == 2) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + `ASSERT(gen_test8.x == 3) + `ASSERT(gen_test8.A.x == 2) + `ASSERT(gen_test8.A.C.x == 1) + `ASSERT(gen_test8.A.B.x == 0) + end + endgenerate + + `ASSERT(x == 3) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + `ASSERT(gen_test8.x == 3) + `ASSERT(gen_test8.A.x == 2) + `ASSERT(gen_test8.A.C.x == 1) + `ASSERT(gen_test8.A.B.x == 0) +endmodule diff --git a/tests/simple/string_format.v b/tests/simple/string_format.v new file mode 100644 index 000000000..ce45ca1e9 --- /dev/null +++ b/tests/simple/string_format.v @@ -0,0 +1,7 @@ +module top; + parameter STR = "something interesting"; + initial begin + $display("A: %s", STR); + $display("B: %0s", STR); + end +endmodule diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv index 022ad56c6..873f7befd 100644 --- a/tests/svtypes/struct_array.sv +++ b/tests/svtypes/struct_array.sv @@ -1,7 +1,7 @@ // test for array indexing in structures module top; - + struct packed { bit [5:0] [7:0] a; // 6 element packed array of bytes bit [15:0] b; // filler for non-zero offset @@ -19,4 +19,24 @@ module top; always_comb assert(s==64'h4200_0012_3400_FFFC); + struct packed { + bit [7:0] [7:0] a; // 8 element packed array of bytes + bit [15:0] b; // filler for non-zero offset + } s2; + + initial begin + s2 = '0; + + s2.a[2:1] = 16'h1234; + s2.a[5] = 8'h42; + + s2.a[7] = '1; + s2.a[7][1:0] = '0; + + s2.b = '1; + s2.b[1:0] = '0; + end + + always_comb assert(s2==80'hFC00_4200_0012_3400_FFFC); + endmodule diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys new file mode 100644 index 000000000..8dd09458e --- /dev/null +++ b/tests/techmap/bug2183.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module foo(inout a, b); + assign a = b; +endmodule +module bar(output c); + foo f(c, 1'b0); +endmodule +EOT + +hierarchy -auto-top +flatten diff --git a/tests/techmap/bug2321.ys b/tests/techmap/bug2321.ys new file mode 100644 index 000000000..637528b21 --- /dev/null +++ b/tests/techmap/bug2321.ys @@ -0,0 +1,15 @@ +read_verilog <<EOT +module m (input i, output o); +wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; "; +endmodule +EOT + +design -stash map + +read_verilog <<EOT +module top(output o); +m m (.o(o), .i(o)); +endmodule +EOT + +techmap -map %map diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys new file mode 100644 index 000000000..ed6b35eb2 --- /dev/null +++ b/tests/techmap/bug2332.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [31:0] a, input signed [2:0] x, output [2:0] o); + +wire [5:0] t = x * 3; +assign o = a >> t; + +endmodule +EOT + +wreduce +equiv_opt -assert peepopt diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys deleted file mode 100644 index 105a89400..000000000 --- a/tests/techmap/dff2dffs.ys +++ /dev/null @@ -1,50 +0,0 @@ -read_verilog << EOT -module top(...); -input clk; -input d; -input sr; -output reg q0, q1, q2, q3, q4, q5; - -initial q0 = 1'b0; -initial q1 = 1'b0; -initial q2 = 1'b1; -initial q3 = 1'b1; -initial q4 = 1'bx; -initial q5 = 1'bx; - -always @(posedge clk) begin - q0 <= sr ? 1'b0 : d; - q1 <= sr ? 1'b1 : d; - q2 <= sr ? 1'b0 : d; - q3 <= sr ? 1'b1 : d; - q4 <= sr ? 1'b0 : d; - q5 <= sr ? 1'b1 : d; -end - -endmodule -EOT - -proc -simplemap -design -save ref - -dff2dffs -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i - -design -load ref -dff2dffs -match-init -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys index eb29680f6..f749e79b2 100644 --- a/tests/techmap/shiftx2mux.ys +++ b/tests/techmap/shiftx2mux.ys @@ -74,12 +74,6 @@ design -save gold design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc -lut 6 select -assert-count 16 t:$lut @@ -92,12 +86,6 @@ sat -verify -prove-asserts -show-ports miter design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc9 -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc9 -lut 6 select -assert-count 16 t:$lut diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 4d3478628..72a3d51eb 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -193,13 +193,13 @@ do elif [ "$frontend" = "verific_gates" ]; then test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext} + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.${refext} test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext} + "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v fi fi fi diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v index 85318562f..3bfff4acd 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.v @@ -23,6 +23,22 @@ module top; end endfunction + function automatic [31:0] operation3; + input [4:0] rounds; + input integer num; + reg [4:0] rounds; + integer i; + begin + begin : shadow + integer rounds; + rounds = 0; + end + for (i = 0; i < rounds; i = i + 1) + num = num * 2; + operation3 = num; + end + endfunction + wire [31:0] a; assign a = 2; @@ -34,11 +50,15 @@ module top; wire [31:0] x2; assign x2 = operation2(A, a); + wire [31:0] x3; + assign x3 = operation3(A, a); + // `define VERIFY `ifdef VERIFY assert property (a == 2); assert property (A == 3); assert property (x1 == 16); assert property (x2 == 4); + assert property (x3 == 16); `endif endmodule diff --git a/tests/various/const_func.v b/tests/various/const_func.v index 76cdc385d..541e63b19 100644 --- a/tests/various/const_func.v +++ b/tests/various/const_func.v @@ -53,6 +53,15 @@ module top(out); c1, c2, c3, c4, d1, d2, d3, d4}; + function signed [31:0] negate; + input integer inp; + negate = ~inp; + endfunction + parameter W = 10; + parameter X = 3; + localparam signed Y = $floor(W / X); + localparam signed Z = negate($floor(W / X)); + // `define VERIFY `ifdef VERIFY assert property (a1 == 0); @@ -71,5 +80,8 @@ module top(out); assert property (d2 == 0); assert property (d3 == 1); assert property (d4 == 1); + + assert property (Y == 3); + assert property (Z == ~3); `endif endmodule diff --git a/tests/various/const_func_block_var.v b/tests/various/const_func_block_var.v new file mode 100644 index 000000000..cb60844ab --- /dev/null +++ b/tests/various/const_func_block_var.v @@ -0,0 +1,26 @@ +module top(out); + function integer operation; + input integer num; + localparam incr = 1; + localparam mult = 1; + begin + operation = 0; + begin : op_i + integer i; + for (i = 0; i * mult < 2; i = i + incr) + begin : op_j + integer j; + localparam other_mult = 2; + for (j = i; j < i * other_mult; j = j + incr) + num = num + incr; + end + num = num * 2; + end + operation = num; + end + endfunction + + localparam res = operation(4); + output wire [31:0] out; + assign out = res; +endmodule diff --git a/tests/various/const_func_block_var.ys b/tests/various/const_func_block_var.ys new file mode 100644 index 000000000..7c2e85c64 --- /dev/null +++ b/tests/various/const_func_block_var.ys @@ -0,0 +1 @@ +read_verilog const_func_block_var.v diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index ee5ad8a1a..45e936a21 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -68,146 +68,3 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 0 t:* - -#################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -clean -select -assert-count 1 t:$dff r:WIDTH=2 %i -select -assert-count 1 t:$mux r:WIDTH=2 %i -select -assert-count 0 t:$dff t:$mux %% t:* %D - -#################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -clean -select -assert-count 1 t:$dff r:WIDTH=2 %i -select -assert-count 1 t:$mux r:WIDTH=2 %i -select -assert-count 0 t:$dff t:$mux %% t:* %D - -################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o); - always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -select -assert-count 1 t:$dff r:WIDTH=2 %i -select -assert-count 1 t:$mux r:WIDTH=2 %i -select -assert-count 0 t:$dff t:$mux %% t:* %D - -################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o); - always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz}; -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -select -assert-count 1 t:$dff r:WIDTH=4 %i -select -assert-count 1 t:$mux r:WIDTH=4 %i -select -assert-count 0 t:$dff t:$mux %% t:* %D - -#################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o); - always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i; -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -wreduce -select -assert-count 1 t:$dff r:WIDTH=2 %i -select -assert-count 2 t:$mux -select -assert-count 2 t:$mux r:WIDTH=2 %i -select -assert-count 0 t:$dff t:$mux %% t:* %D - -#################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); - always @(posedge clk) begin - if (ce) o <= i; - if (!rstn) o <= 4'b1111; - end -endmodule -EOT - -proc -equiv_opt -assert peepopt -design -load postopt -wreduce -select -assert-count 1 t:$dff r:WIDTH=2 %i -select -assert-count 2 t:$mux -select -assert-count 2 t:$mux r:WIDTH=2 %i -select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D - -#################### - -design -reset -read_verilog <<EOT -module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); - initial o <= 4'b0010; - always @(posedge clk) begin - if (ce) o <= i; - if (!rstn) o <= 4'b1111; - end -endmodule -EOT - -proc -# NB: equiv_opt uses equiv_induct which covers -# only the induction half of temporal induction -# --- missing the base-case half -# This makes it akin to `sat -tempinduct-inductonly` -# instead of `sat -tempinduct-baseonly` or -# `sat -tempinduct` which is necessary for this -# testcase -#equiv_opt -assert peepopt - -design -save gold -peepopt -wreduce -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -tempinduct -verify -prove-asserts -show-ports miter - -design -load gate -select -assert-count 1 t:$dff r:WIDTH=4 %i -select -assert-count 2 t:$mux -select -assert-count 2 t:$mux r:WIDTH=4 %i -select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D |