diff options
| -rw-r--r-- | kernel/driver.cc | 4 | ||||
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 46 | 
2 files changed, 46 insertions, 4 deletions
| diff --git a/kernel/driver.cc b/kernel/driver.cc index 02e332f90..a41d0e8cb 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -183,8 +183,8 @@ int main(int argc, char **argv)  		printf("    -b backend\n");  		printf("        use this backend for the output file specified on the command line\n");  		printf("\n"); -		printf("    -f backend\n"); -		printf("        use the specified front for the input files on the command line\n"); +		printf("    -f frontend\n"); +		printf("        use the specified frontend for the input files on the command line\n");  		printf("\n");  		printf("    -H\n");  		printf("        print the command list\n"); diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4602c6cc4..6b5100f75 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -55,10 +55,52 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);  	assign OUT = INIT[{IN3, IN2, IN1, IN0}];  endmodule -module GP4_VDD(output OUT); +module GP_VDD(output OUT);         assign OUT = 1;  endmodule -module GP4_VSS(output OUT); +module GP_VSS(output OUT);         assign OUT = 0;  endmodule + +module GP_LFOSC(input PWRDN, output reg CLKOUT); +	 +	parameter PWRDN_EN = 0; +	parameter AUTO_PWRDN = 0; +	parameter OUT_DIV = 1; +	 +	initial CLKOUT = 0; +	 +	always begin +		if(PWRDN) +			clkout = 0; +		else begin +			//half period of 1730 Hz +			#289017; +			clkout = ~clkout; +		end +	end +	 +endmodule + +module GP_COUNT8(input CLK, input wire RST, output reg OUT); + +	parameter RESET_MODE 	= "RISING";	 +	 +	parameter COUNT_TO		= 8'h1; +	parameter CLKIN_DIVIDE	= 1; +	 +	//more complex hard IP blocks are not supported for simulation yet + +endmodule + +module GP_COUNT14(input CLK, input wire RST, output reg OUT); + +	parameter RESET_MODE 	= "RISING";	 +	 +	parameter COUNT_TO		= 14'h1; +	parameter CLKIN_DIVIDE	= 1; +	 +	//more complex hard IP blocks are not supported for simulation yet + +endmodule | 
