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-rw-r--r--techlibs/ecp5/synth_ecp5.cc2
-rw-r--r--techlibs/ice40/synth_ice40.cc2
-rw-r--r--techlibs/intel_alm/synth_intel_alm.cc1
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
4 files changed, 3 insertions, 4 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 8039531ae..c1545cbb5 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -338,7 +338,7 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args);
if (abc9) {
- run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
+ run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
std::string abc9_opts;
if (nowidelut)
abc9_opts += " -maxlut 4";
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 376cb7dbd..f780832e6 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -387,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
- run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
+ run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index bf9e746b8..0f844961e 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_luts")) {
- run("read_verilog -icells -specify -lib +/abc9_model.v");
run("abc9 -maxlut 6 -W 200");
run("techmap -map +/intel_alm/common/alm_map.v");
run("opt -fast");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c45d389ef..d6ca9e57e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -616,7 +616,7 @@ struct SynthXilinxPass : public ScriptPass
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
- run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
+ run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
if (active_design && active_design->scratchpad.count(k))