diff options
| -rw-r--r-- | techlibs/intel_alm/synth_intel_alm.cc | 2 | ||||
| -rw-r--r-- | tests/arch/intel_alm/dffs.ys | 3 | ||||
| -rw-r--r-- | tests/arch/intel_alm/fsm.ys | 5 |
3 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 0f844961e..6508affc0 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -199,7 +199,7 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_ffs")) { - run("dff2dffe -direct-match $_DFF_*"); + run("dff2dffe"); // As mentioned in common/dff_sim.v, Intel flops power up to zero, // so use `zinit` to add inverters where needed. run("zinit"); diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys index cf29ad8e0..149b3121a 100644 --- a/tests/arch/intel_alm/dffs.ys +++ b/tests/arch/intel_alm/dffs.ys @@ -17,6 +17,5 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT3 %% t:* %D +select -assert-none t:MISTRAL_FF %% t:* %D diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys index 8bb0ebab2..67965569b 100644 --- a/tests/arch/intel_alm/fsm.ys +++ b/tests/arch/intel_alm/fsm.ys @@ -13,6 +13,7 @@ cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:MISTRAL_FF select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1 +select -assert-count 1 t:MISTRAL_ALUT3 select -assert-count 5 t:MISTRAL_ALUT5 -select -assert-count 1 t:MISTRAL_ALUT6 -select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D +select -assert-count 2 t:MISTRAL_ALUT6 +select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D |