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-rw-r--r--techlibs/machxo2/cells_sim.v44
-rw-r--r--techlibs/machxo2/lutrams.txt6
-rw-r--r--techlibs/machxo2/lutrams_map.v43
3 files changed, 72 insertions, 21 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index f69c6d1e9..1e920329c 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -201,6 +201,50 @@ module DCMA (
endmodule
(* abc9_box, lib_whitebox *)
+module TRELLIS_DPR16X4 (
+ input [3:0] DI,
+ input [3:0] WAD,
+ input WRE,
+ input WCK,
+ input [3:0] RAD,
+ output [3:0] DO
+);
+ parameter WCKMUX = "WCK";
+ parameter WREMUX = "WRE";
+ parameter [63:0] INITVAL = 64'h0000000000000000;
+
+ reg [3:0] mem[15:0];
+
+ integer i;
+ initial begin
+ for (i = 0; i < 16; i = i + 1)
+ mem[i] <= INITVAL[4*i +: 4];
+ end
+
+ wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+ reg muxwre;
+ always @(*)
+ case (WREMUX)
+ "1": muxwre = 1'b1;
+ "0": muxwre = 1'b0;
+ "INV": muxwre = ~WRE;
+ default: muxwre = WRE;
+ endcase
+
+ always @(posedge muxwck)
+ if (muxwre)
+ mem[WAD] <= DI;
+
+ assign DO = mem[RAD];
+
+ specify
+ // TODO
+ (RAD *> DO) = 0;
+ endspecify
+endmodule
+
+(* abc9_box, lib_whitebox *)
module DPR16X4C (
input [3:0] DI,
input WCK, WRE,
diff --git a/techlibs/machxo2/lutrams.txt b/techlibs/machxo2/lutrams.txt
index c6b0b6c45..ea42d4fcb 100644
--- a/techlibs/machxo2/lutrams.txt
+++ b/techlibs/machxo2/lutrams.txt
@@ -1,11 +1,11 @@
-ram distributed $__DPR16X4C_ {
+ram distributed $__TRELLIS_DPR16X4_ {
abits 4;
width 4;
cost 4;
- init no_undef;
+ init any;
prune_rom;
port sw "W" {
- clock posedge;
+ clock anyedge;
}
port ar "R" {
}
diff --git a/techlibs/machxo2/lutrams_map.v b/techlibs/machxo2/lutrams_map.v
index b55253fb8..3cb325f04 100644
--- a/techlibs/machxo2/lutrams_map.v
+++ b/techlibs/machxo2/lutrams_map.v
@@ -1,23 +1,30 @@
-module $__DPR16X4C_ (...);
- parameter INIT = 64'b0;
+module $__TRELLIS_DPR16X4_(...);
- input PORT_W_CLK;
- input [3:0] PORT_W_ADDR;
- input [3:0] PORT_W_WR_DATA;
- input PORT_W_WR_EN;
+parameter INIT = 64'bx;
+parameter PORT_W_CLK_POL = 1;
- input [3:0] PORT_R_ADDR;
- output [3:0] PORT_R_RD_DATA;
+input PORT_W_CLK;
+input [3:0] PORT_W_ADDR;
+input [3:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
- DPR16X4C #(
- .INITVAL($sformatf("0x%08x", INIT))
- ) _TECHMAP_REPLACE_ (
- .RAD(PORT_R_ADDR),
- .DO(PORT_R_RD_DATA),
+input [3:0] PORT_R_ADDR;
+output [3:0] PORT_R_RD_DATA;
+
+localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
+
+TRELLIS_DPR16X4 #(
+ .INITVAL(INIT),
+ .WCKMUX(WCKMUX),
+ .WREMUX("WRE")
+) _TECHMAP_REPLACE_ (
+ .RAD(PORT_R_ADDR),
+ .DO(PORT_R_RD_DATA),
+
+ .WAD(PORT_W_ADDR),
+ .DI(PORT_W_WR_DATA),
+ .WCK(PORT_W_CLK),
+ .WRE(PORT_W_WR_EN)
+);
- .WAD(PORT_W_ADDR),
- .DI(PORT_W_WR_DATA),
- .WCK(PORT_W_CLK),
- .WRE(PORT_W_WR_EN)
- );
endmodule