aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Makefile2
-rw-r--r--frontends/ilang/parser.y18
-rw-r--r--frontends/verilog/parser.y14
-rw-r--r--passes/abc/abc.cc53
-rwxr-xr-xtests/tools/autotest.sh3
5 files changed, 73 insertions, 17 deletions
diff --git a/Makefile b/Makefile
index 697cf69fe..9a8a277a5 100644
--- a/Makefile
+++ b/Makefile
@@ -37,7 +37,7 @@ OBJS = kernel/version_$(GIT_REV).o
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = 10cc13a2a0f1
+ABCREV = e97a6e1d59b9
ABCPULL = 1
-include Makefile.conf
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index c2e090220..ebb4d3095 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -87,7 +87,7 @@ design:
module:
TOK_MODULE TOK_ID EOL {
if (current_design->modules.count($2) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of module %s.", $2).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
current_module = new RTLIL::Module;
current_module->name = $2;
current_module->attributes = attrbuf;
@@ -120,7 +120,7 @@ wire_stmt:
attrbuf.clear();
} wire_options TOK_ID EOL {
if (current_module->wires.count($4) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of wire %s.", $4).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
current_wire->name = $4;
current_module->wires[$4] = current_wire;
free($4);
@@ -157,7 +157,7 @@ memory_stmt:
attrbuf.clear();
} memory_options TOK_ID EOL {
if (current_module->memories.count($4) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of memory %s.", $4).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str());
current_memory->name = $4;
current_module->memories[$4] = current_memory;
free($4);
@@ -175,7 +175,7 @@ memory_options:
cell_stmt:
TOK_CELL TOK_ID TOK_ID EOL {
if (current_module->cells.count($3) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of cell %s.", $3).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
current_cell = new RTLIL::Cell;
current_cell->type = $2;
current_cell->name = $3;
@@ -200,7 +200,7 @@ cell_body:
} |
cell_body TOK_CONNECT TOK_ID sigspec EOL {
if (current_cell->connections.count($3) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of cell port %s.", $3).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
current_cell->connections[$3] = *$4;
delete $4;
free($3);
@@ -210,7 +210,7 @@ cell_body:
proc_stmt:
TOK_PROCESS TOK_ID EOL {
if (current_module->processes.count($2) != 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: redefinition of process %s.", $2).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str());
current_process = new RTLIL::Process;
current_process->name = $2;
current_process->attributes = attrbuf;
@@ -362,7 +362,7 @@ sigspec:
} |
TOK_ID {
if (current_module->wires.count($1) == 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: wire %s not found", $1).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.width = current_module->wires[$1]->width;
@@ -374,7 +374,7 @@ sigspec:
} |
TOK_ID '[' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: wire %s not found", $1).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.offset = $3;
@@ -386,7 +386,7 @@ sigspec:
} |
TOK_ID '[' TOK_INT ':' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
- rtlil_frontend_ilang_yyerror(stringf("scope error: wire %s not found", $1).c_str());
+ rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.width = $3 - $5 + 1;
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 5b6bf58c2..8080729b0 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -106,7 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT
-%type <ast> wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
+%type <ast> wire_type range non_opt_range range_or_integer expr basic_expr concat_list rvalue lvalue lvalue_concat_list
%type <string> opt_label tok_prim_wrapper hierarchical_id
%type <boolean> opt_signed
%type <al> attr
@@ -360,6 +360,16 @@ range:
$$ = NULL;
};
+range_or_integer:
+ range {
+ $$ = $1;
+ } |
+ TOK_INTEGER {
+ $$ = new AstNode(AST_RANGE);
+ $$->children.push_back(AstNode::mkconst_int(31, true));
+ $$->children.push_back(AstNode::mkconst_int(0, true));
+ };
+
module_body:
module_body module_body_stmt |
/* empty */;
@@ -380,7 +390,7 @@ task_func_decl:
current_function_or_task = NULL;
ast_stack.pop_back();
} |
- TOK_FUNCTION opt_signed range TOK_ID ';' {
+ TOK_FUNCTION opt_signed range_or_integer TOK_ID ';' {
current_function_or_task = new AstNode(AST_FUNCTION);
current_function_or_task->str = *$4;
ast_stack.back()->children.push_back(current_function_or_task);
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 5aa13572e..e6b7a72d8 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -29,10 +29,10 @@
// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025
// http://en.wikipedia.org/wiki/Topological_sorting
-#define ABC_COMMAND_LIB "strash; retime; balance; dch; map; topo"
-#define ABC_COMMAND_CTR "strash; retime; balance; dch; map; topo; buffer; upsize; dnsize; stime"
-#define ABC_COMMAND_LUT "strash; retime; balance; dch; if"
-#define ABC_COMMAND_DFL "strash; retime; balance; dch; map"
+#define ABC_COMMAND_LIB "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v;"
+#define ABC_COMMAND_CTR "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v; buffer -v; upsize -v; dnsize -v; stime -p"
+#define ABC_COMMAND_LUT "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; if -v"
+#define ABC_COMMAND_DFL "strash; ifraig -v; retime -v; balance -v; dch -vf; scorr -v; map -v"
#include "kernel/register.h"
#include "kernel/sigtools.h"
@@ -359,6 +359,30 @@ static void handle_loops()
fclose(dot_f);
}
+static std::string add_echos_to_abc_cmd(std::string str)
+{
+ std::string new_str, token;
+ for (size_t i = 0; i < str.size(); i++) {
+ token += str[i];
+ if (str[i] == ';') {
+ while (i+1 < str.size() && str[i+1] == ' ')
+ i++;
+ if (!new_str.empty())
+ new_str += "echo; ";
+ new_str += "echo + " + token + " " + token + " ";
+ token.clear();
+ }
+ }
+
+ if (!token.empty()) {
+ if (!new_str.empty())
+ new_str += "echo; echo + " + token + "; ";
+ new_str += token;
+ }
+
+ return new_str;
+}
+
static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str)
{
@@ -398,6 +422,17 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
abc_command = constr_file.empty() ? ABC_COMMAND_LIB : ABC_COMMAND_CTR;
else
abc_command = ABC_COMMAND_DFL;
+ abc_command = add_echos_to_abc_cmd(abc_command);
+
+ if (abc_command.size() > 128) {
+ for (size_t i = 0; i+1 < abc_command.size(); i++)
+ if (abc_command[i] == ';' && abc_command[i+1] == ' ')
+ abc_command[i+1] = '\n';
+ FILE *f = fopen(stringf("%s/abc.script", tempdir_name).c_str(), "wt");
+ fprintf(f, "%s\n", abc_command.c_str());
+ fclose(f);
+ abc_command = stringf("source %s/abc.script", tempdir_name);
+ }
if (clk_str.empty()) {
if (clk_str[0] == '!') {
@@ -578,6 +613,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
exe_file.c_str(), tempdir_name, tempdir_name, abc_command.c_str());
buffer += stringf("write_blif %s/output.blif' 2>&1", tempdir_name);
+ log("%s\n", buffer.c_str());
+
errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand
f = popen(buffer.c_str(), "r");
if (f == NULL)
@@ -838,6 +875,14 @@ struct AbcPass : public Pass {
log(" -constr <file>\n");
log(" pass this file with timing constraints to ABC. use with -liberty.\n");
log("\n");
+ log(" a constr file contains two lines:\n");
+ log(" set_driving_cell <cell_name>\n");
+ log(" set_load <floating_point_number>\n");
+ log("\n");
+ log(" the set_driving_cell statement defines which cell type is assumed to\n");
+ log(" drive the primary inputs and the set_load statement sets the number of\n");
+ log(" flip-flops driven by each primary output.\n");
+ log("\n");
log(" -lut <width>\n");
log(" generate netlist using luts of (max) the specified width.\n");
log("\n");
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 7bccd9a5a..b7ec8b8fe 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -114,7 +114,8 @@ do
test_passes -p "$scriptopt"
else
test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt"
- test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt"
+ # test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt"
+ test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc; opt"
fi
touch ../${bn}.log
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-30 23:33:50 +0000