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-rw-r--r--Makefile2
-rw-r--r--backends/verilog/verilog_backend.cc1
-rw-r--r--frontends/ast/simplify.cc59
-rw-r--r--passes/cmds/chformal.cc19
-rw-r--r--passes/equiv/equiv_make.cc92
-rw-r--r--techlibs/gatemate/cells_bb.v9
-rw-r--r--techlibs/gatemate/cells_sim.v24
-rw-r--r--tests/svinterfaces/resolve_types.sv24
-rw-r--r--tests/svinterfaces/resolve_types.ys6
-rwxr-xr-xtests/svinterfaces/run-test.sh1
-rw-r--r--tests/svtypes/struct_array.sv20
-rw-r--r--tests/various/chformal_coverenable.ys25
-rw-r--r--tests/various/equiv_make_make_assert.ys32
-rw-r--r--tests/xprop/generate.py99
-rw-r--r--tests/xprop/test.py12
15 files changed, 308 insertions, 117 deletions
diff --git a/Makefile b/Makefile
index 227ed419b..5a5772d2a 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LDLIBS += -lrt
endif
endif
-YOSYS_VER := 0.26+4
+YOSYS_VER := 0.26+24
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0a9c0590e..3da168960 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2329,7 +2329,6 @@ struct VerilogBackend : public Backend {
if (!noexpr) {
Pass::call(design, "bmuxmap");
Pass::call(design, "demuxmap");
- Pass::call(design, "bwmuxmap");
}
Pass::call(design, "clean_zerowidth");
log_pop();
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 2dbabca28..f77b59d83 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -278,17 +278,21 @@ static int range_width(AstNode *node, AstNode *rnode)
log_file_error(node->filename, node->location.first_line, "Unpacked array in packed struct/union member %s\n", node->str.c_str());
}
-static void save_struct_array_width(AstNode *node, int width)
+static void save_struct_range_dimensions(AstNode *node, AstNode *rnode)
{
- // stash the stride for the array
- node->multirange_dimensions.push_back(width);
-
+ node->multirange_dimensions.push_back(rnode->range_right);
+ node->multirange_dimensions.push_back(range_width(node, rnode));
+ node->multirange_swapped.push_back(rnode->range_swapped);
}
-static void save_struct_range_swapped(AstNode *node, bool range_swapped)
+static int get_struct_range_offset(AstNode *node, int dimension)
{
- node->multirange_swapped.push_back(range_swapped);
+ return node->multirange_dimensions[2*dimension];
+}
+static int get_struct_range_width(AstNode *node, int dimension)
+{
+ return node->multirange_dimensions[2*dimension + 1];
}
static int size_packed_struct(AstNode *snode, int base_offset)
@@ -322,14 +326,17 @@ static int size_packed_struct(AstNode *snode, int base_offset)
if (node->children[1]->type == AST_RANGE) {
// Unpacked array, e.g. bit [63:0] a [0:3]
auto rnode = node->children[1];
- // C-style array size, e.g. bit [63:0] a [4]
- bool c_type = rnode->children.size() == 1;
- int array_count = c_type ? rnode->range_left : range_width(node, rnode);
- save_struct_array_width(node, array_count);
- save_struct_range_swapped(node, rnode->range_swapped || c_type);
- save_struct_array_width(node, width);
- save_struct_range_swapped(node, node->children[0]->range_swapped);
- width *= array_count;
+ if (rnode->children.size() == 1) {
+ // C-style array size, e.g. bit [63:0] a [4]
+ node->multirange_dimensions.push_back(0);
+ node->multirange_dimensions.push_back(rnode->range_left);
+ node->multirange_swapped.push_back(true);
+ width *= rnode->range_left;
+ } else {
+ save_struct_range_dimensions(node, rnode);
+ width *= range_width(node, rnode);
+ }
+ save_struct_range_dimensions(node, node->children[0]);
}
else {
// The Yosys extension for unpacked arrays in packed structs / unions
@@ -338,8 +345,7 @@ static int size_packed_struct(AstNode *snode, int base_offset)
}
} else {
// Vector
- save_struct_array_width(node, width);
- save_struct_range_swapped(node, node->children[0]->range_swapped);
+ save_struct_range_dimensions(node, node->children[0]);
}
// range nodes are now redundant
for (AstNode *child : node->children)
@@ -355,10 +361,8 @@ static int size_packed_struct(AstNode *snode, int base_offset)
}
width = 1;
for (auto rnode : node->children[0]->children) {
- int rwidth = range_width(node, rnode);
- save_struct_array_width(node, rwidth);
- save_struct_range_swapped(node, rnode->range_swapped);
- width *= rwidth;
+ save_struct_range_dimensions(node, rnode);
+ width *= range_width(node, rnode);
}
// range nodes are now redundant
for (AstNode *child : node->children)
@@ -422,9 +426,14 @@ static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int
{
expr = expr->clone();
+ int offset = get_struct_range_offset(member_node, dimension);
+ if (offset) {
+ expr = new AstNode(AST_SUB, expr, node_int(offset));
+ }
+
if (member_node->multirange_swapped[dimension]) {
// The dimension has swapped range; swap index into the struct accordingly.
- int msb = member_node->multirange_dimensions[dimension] - 1;
+ int msb = get_struct_range_width(member_node, dimension) - 1;
expr = new AstNode(AST_SUB, node_int(msb), expr);
}
@@ -433,7 +442,7 @@ static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int
static AstNode *struct_index_lsb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int &stride)
{
- stride /= member_node->multirange_dimensions[dimension];
+ stride /= get_struct_range_width(member_node, dimension);
auto right = normalize_struct_index(rnode->children.back(), member_node, dimension);
auto offset = stride > 1 ? multiply_by_const(right, stride) : right;
return new AstNode(AST_ADD, lsb_offset, offset);
@@ -1016,7 +1025,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// create name resolution entries for all objects with names
// also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;")
- if (type == AST_MODULE) {
+ if (type == AST_MODULE || type == AST_INTERFACE) {
current_scope.clear();
std::set<std::string> existing;
int counter = 0;
@@ -1701,7 +1710,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
current_filename = filename;
- if (type == AST_MODULE)
+ if (type == AST_MODULE || type == AST_INTERFACE)
current_scope.clear();
// convert defparam nodes to cell parameters
@@ -4691,7 +4700,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
- if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
+ if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg))
children_flags |= AstNode::MEM2REG_FL_ALL;
dict<AstNode*, uint32_t> *proc_flags_p = NULL;
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index 66044b161..da97ff71d 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -55,6 +55,14 @@ struct ChformalPass : public Pass {
log(" -skip <N>\n");
log(" ignore activation of the constraint in the first <N> clock cycles\n");
log("\n");
+ log(" -coverenable\n");
+ log(" add cover statements for the enable signals of the constraints\n");
+ log("\n");
+#ifdef YOSYS_ENABLE_VERIFIC
+ log(" Note: For the Verific frontend it is currently not guaranteed that a\n");
+ log(" reachable SVA statement corresponds to an active enable signal.\n");
+ log("\n");
+#endif
log(" -assert2assume\n");
log(" -assume2assert\n");
log(" -live2fair\n");
@@ -114,6 +122,10 @@ struct ChformalPass : public Pass {
mode_arg = atoi(args[++argidx].c_str());
continue;
}
+ if (mode == 0 && args[argidx] == "-coverenable") {
+ mode = 'p';
+ continue;
+ }
if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") {
assert2assume = true;
mode = 'c';
@@ -263,6 +275,13 @@ struct ChformalPass : public Pass {
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
}
else
+ if (mode =='p')
+ {
+ for (auto cell : constr_cells)
+ module->addCover(NEW_ID_SUFFIX("coverenable"),
+ cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
+ }
+ else
if (mode == 'c')
{
for (auto cell : constr_cells)
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 27cec7549..e15e510be 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -33,6 +33,7 @@ struct EquivMakeWorker
bool inames;
vector<string> blacklists;
vector<string> encfiles;
+ bool make_assert;
pool<IdString> blacklist_names;
dict<IdString, dict<Const, Const>> encdata;
@@ -133,6 +134,12 @@ struct EquivMakeWorker
delete gate_clone;
}
+ void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig)
+ {
+ auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig);
+ equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1);
+ }
+
void find_same_wires()
{
SigMap assign_map(equiv_mod);
@@ -231,15 +238,24 @@ struct EquivMakeWorker
if (gold_wire->port_output || gate_wire->port_output)
{
- Wire *wire = equiv_mod->addWire(id, gold_wire->width);
- wire->port_output = true;
gold_wire->port_input = false;
gate_wire->port_input = false;
gold_wire->port_output = false;
gate_wire->port_output = false;
- for (int i = 0; i < wire->width; i++)
- equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
+ Wire *wire = equiv_mod->addWire(id, gold_wire->width);
+ wire->port_output = true;
+
+ if (make_assert)
+ {
+ add_eq_assertion(gold_wire, gate_wire);
+ equiv_mod->connect(wire, gold_wire);
+ }
+ else
+ {
+ for (int i = 0; i < wire->width; i++)
+ equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
+ }
rd_signal_map.add(assign_map(gold_wire), wire);
rd_signal_map.add(assign_map(gate_wire), wire);
@@ -259,26 +275,31 @@ struct EquivMakeWorker
}
else
{
- Wire *wire = equiv_mod->addWire(id, gold_wire->width);
- SigSpec rdmap_gold, rdmap_gate, rdmap_equiv;
+ if (make_assert)
+ add_eq_assertion(gold_wire, gate_wire);
- for (int i = 0; i < wire->width; i++) {
- if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
- log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
- continue;
- }
- if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
- log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
- continue;
+ else {
+ Wire *wire = equiv_mod->addWire(id, gold_wire->width);
+ SigSpec rdmap_gold, rdmap_gate, rdmap_equiv;
+
+ for (int i = 0; i < wire->width; i++) {
+ if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
+ log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
+ continue;
+ }
+ if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
+ log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
+ continue;
+ }
+ equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
+ rdmap_gold.append(SigBit(gold_wire, i));
+ rdmap_gate.append(SigBit(gate_wire, i));
+ rdmap_equiv.append(SigBit(wire, i));
}
- equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));
- rdmap_gold.append(SigBit(gold_wire, i));
- rdmap_gate.append(SigBit(gate_wire, i));
- rdmap_equiv.append(SigBit(wire, i));
- }
- rd_signal_map.add(rdmap_gold, rdmap_equiv);
- rd_signal_map.add(rdmap_gate, rdmap_equiv);
+ rd_signal_map.add(rdmap_gold, rdmap_equiv);
+ rd_signal_map.add(rdmap_gate, rdmap_equiv);
+ }
}
}
@@ -335,12 +356,20 @@ struct EquivMakeWorker
continue;
}
- for (int i = 0; i < GetSize(gold_sig); i++)
- if (gold_sig[i] != gate_sig[i]) {
- Wire *w = equiv_mod->addWire(NEW_ID);
- equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
- gold_sig[i] = w;
- }
+ if (make_assert)
+ {
+ if (gold_sig != gate_sig)
+ add_eq_assertion(gold_sig, gate_sig);
+ }
+ else
+ {
+ for (int i = 0; i < GetSize(gold_sig); i++)
+ if (gold_sig[i] != gate_sig[i]) {
+ Wire *w = equiv_mod->addWire(NEW_ID);
+ equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
+ gold_sig[i] = w;
+ }
+ }
gold_cell->setPort(gold_conn.first, gold_sig);
}
@@ -417,6 +446,10 @@ struct EquivMakePass : public Pass {
log(" Match FSM encodings using the description from the file.\n");
log(" See 'help fsm_recode' for details.\n");
log("\n");
+ log(" -make_assert\n");
+ log(" Check equivalence with $assert cells instead of $equiv.\n");
+ log(" $eqx (===) is used to compare signals.");
+ log("\n");
log("Note: The circuit created by this command is not a miter (with something like\n");
log("a trigger output), but instead uses $equiv cells to encode the equivalence\n");
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
@@ -427,6 +460,7 @@ struct EquivMakePass : public Pass {
EquivMakeWorker worker;
worker.ct.setup(design);
worker.inames = false;
+ worker.make_assert = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -443,6 +477,10 @@ struct EquivMakePass : public Pass {
worker.encfiles.push_back(args[++argidx]);
continue;
}
+ if (args[argidx] == "-make_assert") {
+ worker.make_assert = true;
+ continue;
+ }
break;
}
diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v
index f6fe6a3e1..87b91764f 100644
--- a/techlibs/gatemate/cells_bb.v
+++ b/techlibs/gatemate/cells_bb.v
@@ -22,6 +22,9 @@ module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
+ parameter LOCK_REQ = 1,
+ parameter CLK270_DOUB = 0,
+ parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
@@ -123,6 +126,12 @@ module CC_CFG_CTRL(
);
endmodule
+(* blackbox *) (* keep *)
+module CC_USR_RSTN (
+ output USR_RSTN
+);
+endmodule
+
(* blackbox *)
module CC_FIFO_40K (
output A_ECC_1B_ERR,
diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v
index 7e88fd7cf..7ed6d83ff 100644
--- a/techlibs/gatemate/cells_sim.v
+++ b/techlibs/gatemate/cells_sim.v
@@ -114,10 +114,10 @@ module CC_LVDS_IBUF #(
parameter [0:0] FF_IBF = 1'bx
)(
(* iopad_external_pin *)
- input IP, IN,
+ input I_P, I_N,
output Y
);
- assign Y = IP;
+ assign Y = I_P;
endmodule
@@ -133,10 +133,10 @@ module CC_LVDS_OBUF #(
)(
input A,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = A;
- assign ON = ~A;
+ assign O_P = A;
+ assign O_N = ~A;
endmodule
@@ -152,10 +152,10 @@ module CC_LVDS_TOBUF #(
)(
input A, T,
(* iopad_external_pin *)
- output OP, ON
+ output O_P, O_N
);
- assign OP = T ? 1'bz : A;
- assign ON = T ? 1'bz : ~A;
+ assign O_P = T ? 1'bz : A;
+ assign O_N = T ? 1'bz : ~A;
endmodule
@@ -174,12 +174,12 @@ module CC_LVDS_IOBUF #(
)(
input A, T,
(* iopad_external_pin *)
- inout IOP, ION,
+ inout IO_P, IO_N,
output Y
);
- assign IOP = T ? 1'bz : A;
- assign ION = T ? 1'bz : ~A;
- assign Y = IOP;
+ assign IO_P = T ? 1'bz : A;
+ assign IO_N = T ? 1'bz : ~A;
+ assign Y = IO_P;
endmodule
diff --git a/tests/svinterfaces/resolve_types.sv b/tests/svinterfaces/resolve_types.sv
new file mode 100644
index 000000000..3c6644e33
--- /dev/null
+++ b/tests/svinterfaces/resolve_types.sv
@@ -0,0 +1,24 @@
+// This test checks that types, including package types, are resolved from within an interface.
+
+typedef logic [7:0] x_t;
+
+package pkg;
+ typedef logic [7:0] y_t;
+endpackage
+
+interface iface;
+ x_t x;
+ pkg::y_t y;
+endinterface
+
+module dut (input logic [7:0] x, output logic [7:0] y);
+ iface intf();
+ assign intf.x = x;
+ assign y = intf.y;
+
+ ondemand u(.intf);
+endmodule
+
+module ref (input logic [7:0] x, output logic [7:0] y);
+ assign y = ~x;
+endmodule
diff --git a/tests/svinterfaces/resolve_types.ys b/tests/svinterfaces/resolve_types.ys
new file mode 100644
index 000000000..a25791f37
--- /dev/null
+++ b/tests/svinterfaces/resolve_types.ys
@@ -0,0 +1,6 @@
+read_verilog -sv resolve_types.sv
+hierarchy -libdir . -check
+flatten
+equiv_make ref dut equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
index 9ef53926c..afa222766 100755
--- a/tests/svinterfaces/run-test.sh
+++ b/tests/svinterfaces/run-test.sh
@@ -4,3 +4,4 @@
./runone.sh svinterface_at_top
./run_simple.sh load_and_derive
+./run_simple.sh resolve_types
diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv
index 739f202ab..a0b84640d 100644
--- a/tests/svtypes/struct_array.sv
+++ b/tests/svtypes/struct_array.sv
@@ -141,6 +141,26 @@ module top;
always_comb assert(s3_llb==80'hFC00_4200_0012_3400_FFFC);
+ struct packed {
+ bit [-10:-3] [-2:-1] [5:2] a;
+ bit [0:15] b; // filler for non-zero offset
+ } s3_off;
+
+ initial begin
+ s3_off = '0;
+
+ s3_off.a[-5:-4] = 16'h1234;
+ s3_off.a[-8] = 8'h42;
+
+ s3_off.a[-10] = '1;
+ s3_off.a[-10][-1][3:0] = '0;
+
+ s3_off.b = '1;
+ s3_off.b[14:15] = '0;
+ end
+
+ always_comb assert(s3_off==80'hFC00_4200_0012_3400_FFFC);
+
`ifndef VERIFIC
// Note that the tests below for unpacked arrays in structs rely on the
// fact that they are actually packed in Yosys.
diff --git a/tests/various/chformal_coverenable.ys b/tests/various/chformal_coverenable.ys
new file mode 100644
index 000000000..52b3ee6bf
--- /dev/null
+++ b/tests/various/chformal_coverenable.ys
@@ -0,0 +1,25 @@
+read_verilog -formal <<EOT
+module top(input a, b, c, d);
+
+ always @* begin
+ if (a) assert (b == c);
+ if (!a) assert (b != c);
+ if (b) assume (c);
+ if (c) cover (d);
+ end
+
+endmodule
+EOT
+
+prep -top top
+
+select -assert-count 1 t:$cover
+
+chformal -cover -coverenable
+select -assert-count 2 t:$cover
+
+chformal -assert -coverenable
+select -assert-count 4 t:$cover
+
+chformal -assume -coverenable
+select -assert-count 5 t:$cover
diff --git a/tests/various/equiv_make_make_assert.ys b/tests/various/equiv_make_make_assert.ys
new file mode 100644
index 000000000..1c2efa723
--- /dev/null
+++ b/tests/various/equiv_make_make_assert.ys
@@ -0,0 +1,32 @@
+read_verilog <<EOT
+module gold(
+ input wire [7:0] a,
+ input wire [7:0] b,
+ output wire [7:0] c
+);
+
+wire [7:0] b_neg;
+assign b_neg = -b;
+assign c = a + b_neg;
+endmodule
+
+module gate(
+ input wire [7:0] a,
+ input wire [7:0] b,
+ output wire [7:0] c
+);
+
+wire [7:0] b_neg;
+assign b_neg = ~b + 1;
+assign c = a + b_neg;
+endmodule
+
+EOT
+
+equiv_make -make_assert gold gate miter
+
+select -assert-count 0 t:$equiv
+select -assert-count 2 t:$assert
+
+prep -top miter
+sat -prove-asserts -verify
diff --git a/tests/xprop/generate.py b/tests/xprop/generate.py
index eef8dc36e..484f1661c 100644
--- a/tests/xprop/generate.py
+++ b/tests/xprop/generate.py
@@ -6,6 +6,7 @@ import argparse
parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
parser.add_argument('-S', '--seed', type=int, help='seed for PRNG')
+parser.add_argument('-m', '--more', action='store_true', help='run more tests')
parser.add_argument('-c', '--count', type=int, default=32, help='number of random patterns to test')
parser.add_argument('-f', '--filter', default='', help='regular expression to filter tests to generate')
args = parser.parse_args()
@@ -32,7 +33,7 @@ def add_test(name, src, seq=False):
print(
f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n"
f"\t@cat {workdir}/status\n"
- # f"\t@grep '^.*: ok' {workdir}/status\n"
+ f"\t@grep '^.*: ok' {workdir}/status\n"
,
file=makefile,
)
@@ -123,50 +124,55 @@ print(".PHONY: all", file=makefile)
print("all:\n\t@echo done\n", file=makefile)
for cell in ["not", "pos", "neg"]:
- unary_test(cell, 1, False, 1)
- unary_test(cell, 3, False, 3)
- unary_test(cell, 3, True, 3)
- unary_test(cell, 3, True, 1)
- unary_test(cell, 3, False, 5)
+ if args.more:
+ unary_test(cell, 1, False, 1)
+ unary_test(cell, 3, False, 3)
+ unary_test(cell, 3, True, 3)
+ unary_test(cell, 3, True, 1)
+ unary_test(cell, 3, False, 5)
unary_test(cell, 3, True, 5)
for cell in ["and", "or", "xor", "xnor"]:
binary_test(cell, 1, 1, False, 1)
binary_test(cell, 1, 1, True, 2)
binary_test(cell, 2, 2, False, 2)
- binary_test(cell, 2, 2, False, 1)
- binary_test(cell, 2, 1, False, 2)
- binary_test(cell, 2, 1, False, 1)
+ if args.more:
+ binary_test(cell, 2, 2, False, 1)
+ binary_test(cell, 2, 1, False, 2)
+ binary_test(cell, 2, 1, False, 1)
# [, "pow"] are not implemented yet
for cell in ["add", "sub", "mul", "div", "mod", "divfloor", "modfloor"]:
- binary_test(cell, 1, 1, False, 1)
- binary_test(cell, 1, 1, False, 2)
- binary_test(cell, 3, 3, False, 1)
- binary_test(cell, 3, 3, False, 3)
- binary_test(cell, 3, 3, False, 6)
- binary_test(cell, 3, 3, True, 1)
- binary_test(cell, 3, 3, True, 3)
- binary_test(cell, 3, 3, True, 6)
+ if args.more:
+ binary_test(cell, 1, 1, False, 1)
+ binary_test(cell, 1, 1, False, 2)
+ binary_test(cell, 3, 3, False, 1)
+ binary_test(cell, 3, 3, False, 3)
+ binary_test(cell, 3, 3, False, 6)
+ binary_test(cell, 3, 3, True, 1)
+ binary_test(cell, 3, 3, True, 3)
+ binary_test(cell, 3, 3, True, 6)
binary_test(cell, 5, 3, False, 3)
binary_test(cell, 5, 3, True, 3)
for cell in ["lt", "le", "eq", "ne", "eqx", "nex", "ge", "gt"]:
- binary_test(cell, 1, 1, False, 1)
- binary_test(cell, 1, 1, False, 2)
- binary_test(cell, 3, 3, False, 1)
- binary_test(cell, 3, 3, False, 2)
- binary_test(cell, 3, 3, True, 1)
- binary_test(cell, 3, 3, True, 2)
- binary_test(cell, 5, 3, False, 1)
- binary_test(cell, 5, 3, True, 1)
+ if args.more:
+ binary_test(cell, 1, 1, False, 1)
+ binary_test(cell, 1, 1, False, 2)
+ binary_test(cell, 3, 3, False, 1)
+ binary_test(cell, 3, 3, False, 2)
+ binary_test(cell, 3, 3, True, 1)
+ binary_test(cell, 3, 3, True, 2)
+ binary_test(cell, 5, 3, False, 1)
+ binary_test(cell, 5, 3, True, 1)
binary_test(cell, 5, 3, False, 2)
binary_test(cell, 5, 3, True, 2)
for cell in ["reduce_and", "reduce_or", "reduce_xor", "reduce_xnor"]:
- unary_test(cell, 1, False, 1)
- unary_test(cell, 3, False, 1)
- unary_test(cell, 3, True, 1)
+ if args.more:
+ unary_test(cell, 1, False, 1)
+ unary_test(cell, 3, False, 1)
+ unary_test(cell, 3, True, 1)
unary_test(cell, 3, False, 3)
unary_test(cell, 3, True, 3)
@@ -183,33 +189,36 @@ for cell in ["logic_and", "logic_or"]:
binary_test(cell, 3, 3, True, 1)
for cell in ["shl", "shr", "sshl", "sshr", "shift"]:
- shift_test(cell, 2, 1, False, False, 2)
- shift_test(cell, 2, 1, True, False, 2)
- shift_test(cell, 2, 1, False, False, 4)
- shift_test(cell, 2, 1, True, False, 4)
- shift_test(cell, 4, 2, False, False, 4)
- shift_test(cell, 4, 2, True, False, 4)
- shift_test(cell, 4, 2, False, False, 8)
- shift_test(cell, 4, 2, True, False, 8)
+ if args.more:
+ shift_test(cell, 2, 1, False, False, 2)
+ shift_test(cell, 2, 1, True, False, 2)
+ shift_test(cell, 2, 1, False, False, 4)
+ shift_test(cell, 2, 1, True, False, 4)
+ shift_test(cell, 4, 2, False, False, 4)
+ shift_test(cell, 4, 2, True, False, 4)
+ shift_test(cell, 4, 2, False, False, 8)
+ shift_test(cell, 4, 2, True, False, 8)
shift_test(cell, 4, 3, False, False, 3)
shift_test(cell, 4, 3, True, False, 3)
for cell in ["shift"]:
- shift_test(cell, 2, 1, False, True, 2)
- shift_test(cell, 2, 1, True, True, 2)
- shift_test(cell, 2, 1, False, True, 4)
- shift_test(cell, 2, 1, True, True, 4)
- shift_test(cell, 4, 2, False, True, 4)
- shift_test(cell, 4, 2, True, True, 4)
+ if args.more:
+ shift_test(cell, 2, 1, False, True, 2)
+ shift_test(cell, 2, 1, True, True, 2)
+ shift_test(cell, 2, 1, False, True, 4)
+ shift_test(cell, 2, 1, True, True, 4)
+ shift_test(cell, 4, 2, False, True, 4)
+ shift_test(cell, 4, 2, True, True, 4)
shift_test(cell, 4, 2, False, True, 8)
shift_test(cell, 4, 2, True, True, 8)
shift_test(cell, 4, 3, False, True, 3)
shift_test(cell, 4, 3, True, True, 3)
for cell in ["shiftx"]:
- shift_test(cell, 2, 1, False, True, 2)
- shift_test(cell, 2, 1, False, True, 4)
- shift_test(cell, 4, 2, False, True, 4)
+ if args.more:
+ shift_test(cell, 2, 1, False, True, 2)
+ shift_test(cell, 2, 1, False, True, 4)
+ shift_test(cell, 4, 2, False, True, 4)
shift_test(cell, 4, 2, False, True, 8)
shift_test(cell, 4, 3, False, True, 3)
diff --git a/tests/xprop/test.py b/tests/xprop/test.py
index 84ad0a1f4..a275b0d93 100644
--- a/tests/xprop/test.py
+++ b/tests/xprop/test.py
@@ -47,7 +47,7 @@ if "clean" in steps:
def yosys(command):
- subprocess.check_call(["yosys", "-Qp", command])
+ subprocess.check_call(["../../../yosys", "-Qp", command])
def remove(file):
try:
@@ -275,7 +275,7 @@ if "prepare" in steps:
file=tb_file,
)
- print(" $finish;", file=tb_file)
+ print(" $finish(0);", file=tb_file)
print("end", file=tb_file)
print("endmodule", file=tb_file)
@@ -344,8 +344,8 @@ for mode in ["", "_xprop"]:
read_rtlil wrapped{mode}.il
chformal -remove
dffunmap
- write_verilog -noparallelcase vsim_expr{mode}.v
write_verilog -noexpr vsim_noexpr{mode}.v
+ write_verilog -noparallelcase vsim_expr{mode}.v
"""
)
@@ -357,15 +357,15 @@ for mode in ["", "_xprop"]:
"-DSIMLIB_FF",
"-DSIMLIB_GLOBAL_CLOCK=top.gclk",
f"-DDUMPFILE=\"vsim_{expr}.vcd\"",
+ "-o",
+ f"vsim_{expr}",
"verilog_sim_tb.v",
f"vsim_{expr}.v",
*simlibs,
- "-o",
- f"vsim_{expr}",
]
)
with open(f"vsim_{expr}.out", "w") as f:
- subprocess.check_call([f"./vsim_{expr}"], stdout=f)
+ subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f)
for mode in ["", "_xprop"]:
if f"sim{mode}" not in steps:
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-13 06:06:24 +0000