diff options
| -rw-r--r-- | tests/arch/machxo2/add_sub.ys | 2 | ||||
| -rw-r--r-- | tests/arch/machxo2/dffs.ys | 8 | ||||
| -rw-r--r-- | tests/arch/machxo2/fsm.ys | 4 | ||||
| -rw-r--r-- | tests/arch/machxo2/logic.ys | 2 | ||||
| -rw-r--r-- | tests/arch/machxo2/mux.ys | 8 | ||||
| -rw-r--r-- | tests/arch/machxo2/shifter.ys | 4 | ||||
| -rw-r--r-- | tests/arch/machxo2/tribuf.ys | 4 |
7 files changed, 16 insertions, 16 deletions
diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys index d9497b818..97ee90fbb 100644 --- a/tests/arch/machxo2/add_sub.ys +++ b/tests/arch/machxo2/add_sub.ys @@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 83a79a9d6..29dcafe23 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -6,8 +6,8 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:FACADE_FF -select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D design -load read hierarchy -top dffe @@ -15,5 +15,5 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 2 t:FACADE_FF t:LUT4 -select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D +select -assert-count 2 t:TRELLIS_FF t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys index 847a61161..a61357fcd 100644 --- a/tests/arch/machxo2/fsm.ys +++ b/tests/arch/machxo2/fsm.ys @@ -11,5 +11,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-max 16 t:LUT4 -select -assert-count 6 t:FACADE_FF -select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D +select -assert-count 6 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys index bf93ab128..0cf57310c 100644 --- a/tests/arch/machxo2/logic.ys +++ b/tests/arch/machxo2/logic.ys @@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 7b7e62d4c..27bffbe63 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux4 @@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux8 @@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux16 @@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux16 # Constrain all select calls below inside the top module select -assert-max 12 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys index 87fdab0fa..bff881fb7 100644 --- a/tests/arch/machxo2/shifter.ys +++ b/tests/arch/machxo2/shifter.ys @@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:FACADE_FF -select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index fce342e18..840979439 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -select -assert-count 3 t:FACADE_IO +select -assert-count 3 t:TRELLIS_IO select -assert-count 1 t:LUT4 -select -assert-none t:FACADE_IO t:LUT4 %% t:* %D +select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D |