diff options
21 files changed, 190 insertions, 190 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 429d23677..429d23677 100755..100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc diff --git a/techlibs/intel/a10gx/cells_arith.v b/techlibs/intel/a10gx/cells_arith.v index 470b686bb..89fb4561f 100755..100644 --- a/techlibs/intel/a10gx/cells_arith.v +++ b/techlibs/intel/a10gx/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule diff --git a/techlibs/intel/a10gx/cells_map.v b/techlibs/intel/a10gx/cells_map.v index 42e7926b8..1430e8551 100755..100644 --- a/techlibs/intel/a10gx/cells_map.v +++ b/techlibs/intel/a10gx/cells_map.v @@ -31,13 +31,13 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function end else if (WIDTH == 2) begin - twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); end /*else if(WIDTH == 3) begin diff --git a/techlibs/intel/a10gx/cells_sim.v b/techlibs/intel/a10gx/cells_sim.v index 1888682ef..e892b377e 100755..100644 --- a/techlibs/intel/a10gx/cells_sim.v +++ b/techlibs/intel/a10gx/cells_sim.v @@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf /* Altera Arria 10 GX LUT Primitive */ module twentynm_lcell_comb (output combout, cout, sumout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); diff --git a/techlibs/intel/common/altpll_bb.v b/techlibs/intel/common/altpll_bb.v index 27eef0f86..d2e6a3643 100644 --- a/techlibs/intel/common/altpll_bb.v +++ b/techlibs/intel/common/altpll_bb.v @@ -19,7 +19,7 @@ /* No clearbox model */ `ifdef NO_CLEARBOX (* blackbox *) -module altpll +module altpll ( inclk, fbin, pllena, @@ -62,7 +62,7 @@ module altpll c2, c3, c4); - + parameter intended_device_family = "MAX 10"; parameter operation_mode = "NORMAL"; parameter pll_type = "AUTO"; @@ -340,7 +340,7 @@ module altpll input phasestep; input configupdate; inout fbmimicbidir; - + output [width_clock-1:0] clk; output [3:0] extclk; @@ -361,6 +361,6 @@ module altpll output fref; output icdrclk; output c0, c1, c2, c3, c4; - + endmodule // altpll `endif diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt index 3bf21afc9..3bf21afc9 100755..100644 --- a/techlibs/intel/common/brams.txt +++ b/techlibs/intel/common/brams.txt diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v index d8413159d..fae4af2ab 100755..100644 --- a/techlibs/intel/common/brams_map.v +++ b/techlibs/intel/common/brams_map.v @@ -2,11 +2,11 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A parameter CFG_ABITS = 8; parameter CFG_DBITS = 36; - parameter ABITS = "1"; - parameter DBITS = "1"; + parameter ABITS = "1"; + parameter DBITS = "1"; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; - + input CLK2; input CLK3; //Read data @@ -19,7 +19,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A input B1EN; wire [CFG_DBITS-1:0] B1DATA_t; - + localparam MODE = CFG_DBITS == 1 ? 1: CFG_DBITS == 2 ? 2: CFG_DBITS == 4 ? 3: @@ -30,7 +30,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A CFG_DBITS == 32 ? 8: CFG_DBITS == 36 ? 9: 'bx; - + localparam NUMWORDS = CFG_DBITS == 1 ? 8192: CFG_DBITS == 2 ? 4096: CFG_DBITS == 4 ? 2048: @@ -41,32 +41,32 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A CFG_DBITS == 32 ? 256: CFG_DBITS == 36 ? 256: 'bx; - - altsyncram #(.clock_enable_input_b ("ALTERNATE" ), - .clock_enable_input_a ("ALTERNATE" ), - .clock_enable_output_b ("NORMAL" ), - .clock_enable_output_a ("NORMAL" ), - .wrcontrol_aclr_a ("NONE" ), - .indata_aclr_a ("NONE" ), - .address_aclr_a ("NONE" ), - .outdata_aclr_a ("NONE" ), - .outdata_reg_a ("UNREGISTERED"), - .operation_mode ("SINGLE_PORT" ), - .intended_device_family ("CYCLONE IVE" ), - .outdata_reg_a ("UNREGISTERED"), - .lpm_type ("altsyncram" ), - .init_type ("unused" ), + + altsyncram #(.clock_enable_input_b ("ALTERNATE" ), + .clock_enable_input_a ("ALTERNATE" ), + .clock_enable_output_b ("NORMAL" ), + .clock_enable_output_a ("NORMAL" ), + .wrcontrol_aclr_a ("NONE" ), + .indata_aclr_a ("NONE" ), + .address_aclr_a ("NONE" ), + .outdata_aclr_a ("NONE" ), + .outdata_reg_a ("UNREGISTERED"), + .operation_mode ("SINGLE_PORT" ), + .intended_device_family ("CYCLONE IVE" ), + .outdata_reg_a ("UNREGISTERED"), + .lpm_type ("altsyncram" ), + .init_type ("unused" ), .ram_block_type ("AUTO" ), .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value .power_up_uninitialized ("FALSE"), .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value .width_byteena_a (1), // Forced value - .numwords_b ( NUMWORDS ), - .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_ABITS ), - .width_b ( CFG_DBITS ), - .widthad_a ( CFG_ABITS ), - .width_a ( CFG_DBITS ) + .numwords_b ( NUMWORDS ), + .numwords_a ( NUMWORDS ), + .widthad_b ( CFG_ABITS ), + .width_b ( CFG_DBITS ), + .widthad_a ( CFG_ABITS ), + .width_a ( CFG_DBITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), @@ -78,16 +78,16 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A .wren_b(1'b0), .rden_b(1'b0), .q_b(1'b0), - .clock0(CLK2), + .clock0(CLK2), .clock1(1'b1), // Unused in single port mode .clocken0(1'b1), .clocken1(1'b1), .clocken2(1'b1), .clocken3(1'b1), - .aclr0(1'b0), + .aclr0(1'b0), .aclr1(1'b0), .addressstall_a(1'b0), .addressstall_b(1'b0)); - + endmodule diff --git a/techlibs/intel/common/m9k_bb.v b/techlibs/intel/common/m9k_bb.v index 4370a105e..b18a752f5 100755..100644 --- a/techlibs/intel/common/m9k_bb.v +++ b/techlibs/intel/common/m9k_bb.v @@ -17,10 +17,10 @@ * */ (* blackbox *) -module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, - q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, +module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, + q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, addressstall_a, addressstall_b); - + parameter clock_enable_input_b = "ALTERNATE"; parameter clock_enable_input_a = "ALTERNATE"; parameter clock_enable_output_b = "NORMAL"; @@ -33,7 +33,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr parameter operation_mode = "SINGLE_PORT"; parameter intended_device_family = "MAX 10 FPGA"; parameter outdata_reg_a = "UNREGISTERED"; - parameter lpm_type = "altsyncram"; + parameter lpm_type = "altsyncram"; parameter init_type = "unused"; parameter ram_block_type = "AUTO"; parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; @@ -46,7 +46,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr parameter width_b = 1; parameter widthad_a = 1; parameter width_a = 1; - + // Port A declarations output [35:0] q_a; input [35:0] data_a; @@ -66,5 +66,5 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr input addressstall_a; input addressstall_b; // TODO: Implement the correct simulation model - + endmodule // altsyncram diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v index 555b91599..010a4b5da 100755..100644 --- a/techlibs/intel/cycloneiv/cells_arith.v +++ b/techlibs/intel/cycloneiv/cells_arith.v @@ -19,7 +19,7 @@ // NOTE: This is still WIP. (* techmap_celltype = "$alu" *) -/* Uncomment this for LCU???? +/* Uncomment this for LCU???? module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -46,7 +46,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ //cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); /* @@ -61,7 +61,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ /*assign X = AA ^ BB; - + endmodule*/ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; @@ -86,7 +86,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; - + cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); genvar i; generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v index 4db91d926..b991fbae7 100755..100644 --- a/techlibs/intel/cycloneiv/cells_map.v +++ b/techlibs/intel/cycloneiv/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -62,7 +62,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function diff --git a/techlibs/intel/cycloneiv/cells_sim.v b/techlibs/intel/cycloneiv/cells_sim.v index a2891d6e4..2af2ab990 100755..100644 --- a/techlibs/intel/cycloneiv/cells_sim.v +++ b/techlibs/intel/cycloneiv/cells_sim.v @@ -26,7 +26,7 @@ module GND (output G); endmodule // GND /* Altera Cyclone IV (GX) devices Input Buffer Primitive */ -module cycloneiv_io_ibuf +module cycloneiv_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; @@ -40,7 +40,7 @@ module cycloneiv_io_obuf endmodule // fiftyfivenm_io_obuf /* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */ -module cycloneiv_lcell_comb +module cycloneiv_lcell_comb (output combout, cout, input dataa, datab, datac, datad, cin); @@ -113,7 +113,7 @@ module cycloneiv_lcell_comb endmodule // cycloneiv_lcell_comb /* Altera D Flip-Flop Primitive */ -module dffeas +module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); @@ -125,7 +125,7 @@ module dffeas reg q_tmp; wire reset; reg [7:0] debug_net; - + assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; @@ -134,7 +134,7 @@ module dffeas else q_tmp <= d; end assign q = q_tmp; - + endmodule // dffeas /* Cyclone IV GX altpll clearbox model */ @@ -177,9 +177,9 @@ module cycloneiv_pll parameter bandwidth = 0; parameter bandwidth_type = "auto"; parameter use_dc_coupling = "false"; - parameter lock_high = 0; - parameter lock_low = 0; - parameter lock_window_ui = "0.05"; + parameter lock_high = 0; + parameter lock_low = 0; + parameter lock_window_ui = "0.05"; parameter test_bypass_lock_detect = "off"; parameter clk0_output_frequency = 0; parameter clk0_multiply_by = 0; @@ -258,16 +258,16 @@ module cycloneiv_pll parameter c4_test_source = -1; parameter vco_multiply_by = 0; parameter vco_divide_by = 0; - parameter vco_post_scale = 1; + parameter vco_post_scale = 1; parameter vco_frequency_control = "auto"; parameter vco_phase_shift_step = 0; parameter charge_pump_current = 10; - parameter loop_filter_r = "1.0"; - parameter loop_filter_c = 0; + parameter loop_filter_r = "1.0"; + parameter loop_filter_c = 0; parameter pll_compensation_delay = 0; parameter lpm_type = "cycloneiv_pll"; parameter phase_counter_select_width = 3; - + input [1:0] inclk; input fbin; input clkswitch; @@ -280,7 +280,7 @@ module cycloneiv_pll input scanclkena; input scandata; input configupdate; - + output [4:0] clk; output [1:0] clkbad; output activeclock; @@ -293,7 +293,7 @@ module cycloneiv_pll output vcounderrange; output fref; output icdrclk; - + endmodule // cycloneive_pll diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v index 3eaec3715..634cec789 100755..100644 --- a/techlibs/intel/cycloneive/arith_map.v +++ b/techlibs/intel/cycloneive/arith_map.v @@ -40,7 +40,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; - + cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); genvar i; generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice @@ -48,5 +48,5 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); end endgenerate assign X = AA ^ BB; - + endmodule diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v index e7477773a..bf87f5525 100755..100644 --- a/techlibs/intel/cycloneive/cells_map.v +++ b/techlibs/intel/cycloneive/cells_map.v @@ -38,7 +38,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -61,38 +61,38 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function end else if (WIDTH == 2) begin - cycloneive_lcell_comb #(.lut_mask({4{LUT}}), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cycloneive_lcell_comb #(.lut_mask({4{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(1'b1), .datad(1'b1)); end else if(WIDTH == 3) begin - cycloneive_lcell_comb #(.lut_mask({2{LUT}}), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cycloneive_lcell_comb #(.lut_mask({2{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), .datad(1'b1)); end else if(WIDTH == 4) begin - cycloneive_lcell_comb #(.lut_mask(LUT), - .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cycloneive_lcell_comb #(.lut_mask(LUT), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), .datad(A[3])); end else wire _TECHMAP_FAIL_ = 1; endgenerate - -endmodule + +endmodule diff --git a/techlibs/intel/cycloneive/cells_sim.v b/techlibs/intel/cycloneive/cells_sim.v index 23d06bc1e..f17b86fdf 100755..100644 --- a/techlibs/intel/cycloneive/cells_sim.v +++ b/techlibs/intel/cycloneive/cells_sim.v @@ -25,21 +25,21 @@ module GND (output G); endmodule // GND /* Altera Cyclone IV (E) devices Input Buffer Primitive */ -module cycloneive_io_ibuf +module cycloneive_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; endmodule // fiftyfivenm_io_ibuf /* Altera Cyclone IV (E) devices Output Buffer Primitive */ -module cycloneive_io_obuf +module cycloneive_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; endmodule // fiftyfivenm_io_obuf /* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */ -module cycloneive_lcell_comb +module cycloneive_lcell_comb (output combout, cout, input dataa, datab, datac, datad, cin); @@ -112,7 +112,7 @@ module cycloneive_lcell_comb endmodule // cycloneive_lcell_comb /* Altera D Flip-Flop Primitive */ -module dffeas +module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); @@ -124,7 +124,7 @@ module dffeas reg q_tmp; wire reset; reg [7:0] debug_net; - + assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; @@ -133,7 +133,7 @@ module dffeas else q_tmp <= d; end assign q = q_tmp; - + endmodule // dffeas /* Cyclone IV E altpll clearbox model */ @@ -174,9 +174,9 @@ module cycloneive_pll parameter bandwidth = 0; parameter bandwidth_type = "auto"; parameter use_dc_coupling = "false"; - parameter lock_high = 0; - parameter lock_low = 0; - parameter lock_window_ui = "0.05"; + parameter lock_high = 0; + parameter lock_low = 0; + parameter lock_window_ui = "0.05"; parameter test_bypass_lock_detect = "off"; parameter clk0_output_frequency = 0; parameter clk0_multiply_by = 0; @@ -255,16 +255,16 @@ module cycloneive_pll parameter c4_test_source = -1; parameter vco_multiply_by = 0; parameter vco_divide_by = 0; - parameter vco_post_scale = 1; + parameter vco_post_scale = 1; parameter vco_frequency_control = "auto"; parameter vco_phase_shift_step = 0; parameter charge_pump_current = 10; - parameter loop_filter_r = "1.0"; - parameter loop_filter_c = 0; + parameter loop_filter_r = "1.0"; + parameter loop_filter_c = 0; parameter pll_compensation_delay = 0; parameter lpm_type = "cycloneive_pll"; parameter phase_counter_select_width = 3; - + input [1:0] inclk; input fbin; input clkswitch; @@ -288,5 +288,5 @@ module cycloneive_pll output phasedone; output vcooverrange; output vcounderrange; - + endmodule // cycloneive_pll diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v index 470b686bb..89fb4561f 100755..100644 --- a/techlibs/intel/cyclonev/cells_arith.v +++ b/techlibs/intel/cyclonev/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index b3927ea4a..9fe8db2da 100755..100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -60,89 +60,89 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function - end + end else if (WIDTH == 2) begin - cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(1'b1), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), + .datad(1'b1), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 3) begin - cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), + .datad(1'b1), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 4) begin - cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(1'b1), - .dataf(1'b1), + .datad(A[3]), + .datae(1'b1), + .dataf(1'b1), .datag(1'b1)); - end + end else - if(WIDTH == 5) begin + if(WIDTH == 5) begin cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(1'b1), + .datad(A[3]), + .datae(A[4]), + .dataf(1'b1), .datag(1'b1)); - end + end else if(WIDTH == 6) begin cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), + .datad(A[3]), + .datae(A[4]), + .dataf(A[5]), .datag(1'b1)); - end + end else if(WIDTH == 7) begin cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), + _TECHMAP_REPLACE_ + (.combout(Y), + .dataa(A[0]), + .datab(A[1]), .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), + .datad(A[3]), + .datae(A[4]), + .dataf(A[5]), .datag(A[6])); - end + end else wire _TECHMAP_FAIL_ = 1; endgenerate diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v index 363310e54..5ecdabcfc 100755..100644 --- a/techlibs/intel/cyclonev/cells_sim.v +++ b/techlibs/intel/cyclonev/cells_sim.v @@ -25,23 +25,23 @@ module GND (output G); endmodule // GND /* Altera Cyclone V devices Input Buffer Primitive */ -module cyclonev_io_ibuf +module cyclonev_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; endmodule // cyclonev_io_ibuf /* Altera Cyclone V devices Output Buffer Primitive */ -module cyclonev_io_obuf +module cyclonev_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; endmodule // cyclonev_io_obuf /* Altera Cyclone V LUT Primitive */ -module cyclonev_lcell_comb +module cyclonev_lcell_comb (output combout, cout, sumout, shareout, - input dataa, datab, datac, datad, + input dataa, datab, datac, datad, input datae, dataf, datag, cin, input sharein); @@ -59,8 +59,8 @@ module cyclonev_lcell_comb // Extended mode uses mux to define the output wire mux_0, mux_1; // Input for hold the shared LUT mode value - wire shared_lut_alm; - + wire shared_lut_alm; + // Simulation model of 4-input LUT function lut4; input [15:0] mask; @@ -75,7 +75,7 @@ module cyclonev_lcell_comb lut4 = dataa ? s1[1] : s1[0]; end endfunction // lut4 - + // Simulation model of 5-input LUT function lut5; input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer. @@ -119,7 +119,7 @@ endmodule // cyclonev_lcell_comb /* Altera D Flip-Flop Primitive */ -module dffeas +module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); @@ -131,7 +131,7 @@ module dffeas reg q_tmp; wire reset; reg [7:0] debug_net; - + assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; @@ -140,5 +140,5 @@ module dffeas else q_tmp <= d; end assign q = q_tmp; - + endmodule // dffeas diff --git a/techlibs/intel/max10/cells_arith.v b/techlibs/intel/max10/cells_arith.v index 9ef073f7c..e2194cbd7 100755..100644 --- a/techlibs/intel/max10/cells_arith.v +++ b/techlibs/intel/max10/cells_arith.v @@ -45,10 +45,10 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); //wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] C = {COx, CI}; - + /* Start implementation */ (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - + genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice if(i==Y_WIDTH-1) begin @@ -61,5 +61,5 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO); endgenerate /* End implementation */ assign X = AA ^ BB; - -endmodule + +endmodule diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v index b74007ff8..9229fae51 100755..100644 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); +module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; wire E_i = ~ E; dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); @@ -62,7 +62,7 @@ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; input [WIDTH-1:0] A; - output Y; + output Y; generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function diff --git a/techlibs/intel/max10/cells_sim.v b/techlibs/intel/max10/cells_sim.v index 29dd8fce4..98673596b 100755..100644 --- a/techlibs/intel/max10/cells_sim.v +++ b/techlibs/intel/max10/cells_sim.v @@ -26,21 +26,21 @@ module GND (output G); endmodule // GND /* Altera MAX10 devices Input Buffer Primitive */ -module fiftyfivenm_io_ibuf +module fiftyfivenm_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; endmodule // fiftyfivenm_io_ibuf /* Altera MAX10 devices Output Buffer Primitive */ -module fiftyfivenm_io_obuf +module fiftyfivenm_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; endmodule // fiftyfivenm_io_obuf /* Altera MAX10 4-input non-fracturable LUT Primitive */ -module fiftyfivenm_lcell_comb +module fiftyfivenm_lcell_comb (output combout, cout, input dataa, datab, datac, datad, cin); @@ -113,7 +113,7 @@ module fiftyfivenm_lcell_comb endmodule // fiftyfivenm_lcell_comb /* Altera D Flip-Flop Primitive */ -module dffeas +module dffeas (output q, input d, clk, clrn, prn, ena, input asdata, aload, sclr, sload); @@ -125,7 +125,7 @@ module dffeas reg q_tmp; wire reset; reg [7:0] debug_net; - + assign reset = (prn && sclr && ~clrn && ena); assign q = q_tmp & 1'b1; @@ -134,7 +134,7 @@ module dffeas else q_tmp <= d; end assign q = q_tmp; - + endmodule // dffeas /* MAX10 altpll clearbox model */ @@ -175,9 +175,9 @@ module fiftyfivenm_pll parameter bandwidth = 0; parameter bandwidth_type = "auto"; parameter use_dc_coupling = "false"; - parameter lock_high = 0; - parameter lock_low = 0; - parameter lock_window_ui = "0.05"; + parameter lock_high = 0; + parameter lock_low = 0; + parameter lock_window_ui = "0.05"; parameter test_bypass_lock_detect = "off"; parameter clk0_output_frequency = 0; parameter clk0_multiply_by = 0; @@ -256,16 +256,16 @@ module fiftyfivenm_pll parameter c4_test_source = -1; parameter vco_multiply_by = 0; parameter vco_divide_by = 0; - parameter vco_post_scale = 1; + parameter vco_post_scale = 1; parameter vco_frequency_control = "auto"; parameter vco_phase_shift_step = 0; parameter charge_pump_current = 10; - parameter loop_filter_r = "1.0"; - parameter loop_filter_c = 0; + parameter loop_filter_r = "1.0"; + parameter loop_filter_c = 0; parameter pll_compensation_delay = 0; parameter lpm_type = "fiftyfivenm_pll"; parameter phase_counter_select_width = 3; - + input [1:0] inclk; input fbin; input clkswitch; @@ -288,5 +288,5 @@ module fiftyfivenm_pll output phasedone; output vcooverrange; output vcounderrange; - + endmodule // cycloneive_pll diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 5f8b9c92a..9e4b33601 100755..100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -170,7 +170,7 @@ struct SynthIntelPass : public ScriptPass { { run("synth -run coarse"); } - + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/intel/common/brams.txt"); @@ -179,7 +179,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("fine")) { - run("opt -fast -mux_undef -undriven -fine -full"); + run("opt -fast -mux_undef -undriven -fine -full"); run("memory_map"); run("opt -undriven -fine"); run("dffsr2dff"); @@ -209,7 +209,7 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/intel/max10/cells_map.v"); else if(family_opt=="a10gx") run("techmap -map +/intel/a10gx/cells_map.v"); - else if(family_opt=="cyclonev") + else if(family_opt=="cyclonev") run("techmap -map +/intel/cyclonev/cells_map.v"); else if(family_opt=="cycloneiv") run("techmap -map +/intel/cycloneiv/cells_map.v"); |