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-rw-r--r--passes/equiv/equiv_struct.cc23
1 files changed, 22 insertions, 1 deletions
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index c509e2556..d231913c2 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -116,9 +116,15 @@ struct EquivStructWorker
{
log(" Starting new iteration.\n");
+ pool<SigBit> equiv_inputs;
+
for (auto cell : module->selected_cells())
if (cell->type == "$equiv") {
- equiv_bits.add(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\B")));
+ SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
+ SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
+ equiv_bits.add(sig_b, sig_a);
+ equiv_inputs.insert(sig_a);
+ equiv_inputs.insert(sig_b);
cells_by_type[cell->type].insert(cell->name);
} else
if (module->design->selected(module, cell)) {
@@ -126,6 +132,21 @@ struct EquivStructWorker
cells_by_type[cell->type].insert(cell->name);
}
+ for (auto cell_name : cells_by_type["$equiv"]) {
+ Cell *cell = module->cell(cell_name);
+ SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
+ SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
+ SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
+ if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
+ log(" Purging redundant $equiv cell %s.\n", log_id(cell));
+ module->remove(cell);
+ merge_count++;
+ }
+ }
+
+ if (merge_count > 0)
+ return;
+
for (auto &it : cells_by_type)
{
if (it.second.size() <= 1)