diff options
| -rw-r--r-- | techlibs/common/stdcells.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v index ca73f5bcd..e37ad20d5 100644 --- a/techlibs/common/stdcells.v +++ b/techlibs/common/stdcells.v @@ -351,9 +351,15 @@ endgenerate assign buffer[0] = A[0]; \$_INV_ gate_inv ( .A(buffer[A_WIDTH-1]), - .Y(Y) + .Y(Y[0]) ); +generate + if (Y_WIDTH > 1) begin:V + assign Y[Y_WIDTH-1:1] = 0; + end +endgenerate + endmodule // -------------------------------------------------------- |