diff options
43 files changed, 679 insertions, 232 deletions
@@ -82,7 +82,7 @@ all: top-all YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) -CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_ -fPIC -I$(PREFIX)/include +CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include LDLIBS := $(LDLIBS) -lstdc++ -lm PLUGIN_LDFLAGS := @@ -123,7 +123,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.9+3496 +YOSYS_VER := 0.9+3547 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o @@ -593,7 +593,7 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,libs/json11/json11.hpp)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) -$(eval $(call add_include_file,backends/ilang/ilang_backend.h)) +$(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc)) @@ -634,7 +634,7 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc else include $(YOSYS_SRC)/frontends/verilog/Makefile.inc -include $(YOSYS_SRC)/frontends/ilang/Makefile.inc +include $(YOSYS_SRC)/frontends/rtlil/Makefile.inc include $(YOSYS_SRC)/frontends/ast/Makefile.inc include $(YOSYS_SRC)/frontends/blif/Makefile.inc @@ -651,7 +651,7 @@ include $(YOSYS_SRC)/passes/opt/Makefile.inc include $(YOSYS_SRC)/passes/techmap/Makefile.inc include $(YOSYS_SRC)/backends/verilog/Makefile.inc -include $(YOSYS_SRC)/backends/ilang/Makefile.inc +include $(YOSYS_SRC)/backends/rtlil/Makefile.inc include $(YOSYS_SRC)/techlibs/common/Makefile.inc diff --git a/backends/ilang/Makefile.inc b/backends/ilang/Makefile.inc deleted file mode 100644 index 52fc2b891..000000000 --- a/backends/ilang/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ - -OBJS += backends/ilang/ilang_backend.o - diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 98a14173b..a6b36de6c 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -59,7 +59,7 @@ struct IntersynthBackend : public Backend { log(" do not generate celltypes and conntypes commands. i.e. just output\n"); log(" the netlists. this is used for postsilicon synthesis.\n"); log("\n"); - log(" -lib <verilog_or_ilang_file>\n"); + log(" -lib <verilog_or_rtlil_file>\n"); log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); @@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); } diff --git a/backends/rtlil/Makefile.inc b/backends/rtlil/Makefile.inc new file mode 100644 index 000000000..f691282ca --- /dev/null +++ b/backends/rtlil/Makefile.inc @@ -0,0 +1,3 @@ + +OBJS += backends/rtlil/rtlil_backend.o + diff --git a/backends/ilang/ilang_backend.cc b/backends/rtlil/rtlil_backend.cc index aa5a175ca..01b4bde53 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -18,19 +18,19 @@ * --- * * A very simple and straightforward backend for the RTLIL text - * representation (as understood by the 'ilang' frontend). + * representation. * */ -#include "ilang_backend.h" +#include "rtlil_backend.h" #include "kernel/yosys.h" #include <errno.h> USING_YOSYS_NAMESPACE -using namespace ILANG_BACKEND; +using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN -void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) +void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) width = data.bits.size() - offset; @@ -83,7 +83,7 @@ void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int wi } } -void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint) +void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, autoint); @@ -97,7 +97,7 @@ void ILANG_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, } } -void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint) +void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint) { if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk(), autoint); @@ -111,7 +111,7 @@ void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo } } -void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) +void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { for (auto &it : wire->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -136,7 +136,7 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s\n", wire->name.c_str()); } -void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) +void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { for (auto &it : memory->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -153,7 +153,7 @@ void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL f << stringf("%s\n", memory->name.c_str()); } -void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) +void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { for (auto &it : cell->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); @@ -177,7 +177,7 @@ void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) +void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) { @@ -192,7 +192,7 @@ void ILANG_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, con dump_proc_switch(f, indent, *it); } -void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) +void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); @@ -225,7 +225,7 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy) +void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy) { f << stringf("%s" "sync ", indent.c_str()); switch (sy->type) { @@ -251,7 +251,7 @@ void ILANG_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT } } -void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) +void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); @@ -265,7 +265,7 @@ void ILANG_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL:: f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) +void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { f << stringf("%s" "connect ", indent.c_str()); dump_sigspec(f, left); @@ -274,7 +274,7 @@ void ILANG_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } -void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { bool print_header = flag_m || design->selected_whole_module(module->name); bool print_body = !flag_n || !design->selected_whole_module(module->name); @@ -360,7 +360,7 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu f << stringf("%s" "end\n", indent.c_str()); } -void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { int init_autoidx = autoidx; @@ -396,15 +396,15 @@ void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN -struct IlangBackend : public Backend { - IlangBackend() : Backend("ilang", "write design to ilang file") { } +struct RTLILBackend : public Backend { + RTLILBackend() : Backend("rtlil", "write design to RTLIL file") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" write_ilang [filename]\n"); + log(" write_rtlil [filename]\n"); log("\n"); - log("Write the current design to an 'ilang' file. (ilang is a text representation\n"); + log("Write the current design to an RTLIL file. (RTLIL is a text representation\n"); log("of a design in yosys's internal format.)\n"); log("\n"); log(" -selected\n"); @@ -415,7 +415,7 @@ struct IlangBackend : public Backend { { bool selected = false; - log_header(design, "Executing ILANG backend.\n"); + log_header(design, "Executing RTLIL backend.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -432,12 +432,27 @@ struct IlangBackend : public Backend { log("Output filename: %s\n", filename.c_str()); *f << stringf("# Generated by %s\n", yosys_version_str); - ILANG_BACKEND::dump_design(*f, design, selected, true, false); + RTLIL_BACKEND::dump_design(*f, design, selected, true, false); + } +} RTLILBackend; + +struct IlangBackend : public Backend { + IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log("See `help write_rtlil`.\n"); + log("\n"); + } + void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override + { + RTLILBackend.execute(f, filename, args, design); } } IlangBackend; struct DumpPass : public Pass { - DumpPass() : Pass("dump", "print parts of the design in ilang format") { } + DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -445,7 +460,7 @@ struct DumpPass : public Pass { log(" dump [options] [selection]\n"); log("\n"); log("Write the selected parts of the design to the console or specified file in\n"); - log("ilang format.\n"); + log("RTLIL format.\n"); log("\n"); log(" -m\n"); log(" also dump the module headers, even if only parts of a single\n"); @@ -508,7 +523,7 @@ struct DumpPass : public Pass { f = &buf; } - ILANG_BACKEND::dump_design(*f, design, true, flag_m, flag_n); + RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n); if (!filename.empty()) { delete f; diff --git a/backends/ilang/ilang_backend.h b/backends/rtlil/rtlil_backend.h index 97dcbb628..77eea353c 100644 --- a/backends/ilang/ilang_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -18,19 +18,19 @@ * --- * * A very simple and straightforward backend for the RTLIL text - * representation (as understood by the 'ilang' frontend). + * representation. * */ -#ifndef ILANG_BACKEND_H -#define ILANG_BACKEND_H +#ifndef RTLIL_BACKEND_H +#define RTLIL_BACKEND_H #include "kernel/yosys.h" #include <stdio.h> YOSYS_NAMESPACE_BEGIN -namespace ILANG_BACKEND { +namespace RTLIL_BACKEND { void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index a79c0bd99..4a53ce6d5 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -824,38 +824,49 @@ struct Smt2Worker is_register = true; if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) { RTLIL::SigSpec sig = sigmap(wire); + std::vector<std::string> comments; if (wire->port_input) - decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); if (wire->port_output) - decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); if (is_register) - decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) - decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); + comments.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig))) - decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), + comments.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), clock_posedge.count(sig) ? " posedge" : "", clock_negedge.count(sig) ? " negedge" : "")); if (bvmode && GetSize(sig) > 1) { + std::string sig_bv = get_bv(sig); + if (!comments.empty()) + decls.insert(decls.end(), comments.begin(), comments.end()); decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) (_ BitVec %d) %s)\n", - get_id(module), get_id(wire), get_id(module), GetSize(sig), get_bv(sig).c_str())); + get_id(module), get_id(wire), get_id(module), GetSize(sig), sig_bv.c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))", get_id(module), get_id(wire), get_id(module), get_id(wire))); } else { - for (int i = 0; i < GetSize(sig); i++) + std::vector<std::string> sig_bool; + for (int i = 0; i < GetSize(sig); i++) { + sig_bool.push_back(get_bool(sig[i])); + } + if (!comments.empty()) + decls.insert(decls.end(), comments.begin(), comments.end()); + for (int i = 0; i < GetSize(sig); i++) { if (GetSize(sig) > 1) { decls.push_back(stringf("(define-fun |%s_n %s %d| ((state |%s_s|)) Bool %s)\n", - get_id(module), get_id(wire), i, get_id(module), get_bool(sig[i]).c_str())); + get_id(module), get_id(wire), i, get_id(module), sig_bool[i].c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s %d| state) (|%s_n %s %d| other_state))", get_id(module), get_id(wire), i, get_id(module), get_id(wire), i)); } else { decls.push_back(stringf("(define-fun |%s_n %s| ((state |%s_s|)) Bool %s)\n", - get_id(module), get_id(wire), get_id(module), get_bool(sig[i]).c_str())); + get_id(module), get_id(wire), get_id(module), sig_bool[i].c_str())); if (wire->port_input) ex_input_eq.push_back(stringf(" (= (|%s_n %s| state) (|%s_n %s| other_state))", get_id(module), get_id(wire), get_id(module), get_id(wire))); } + } } } } @@ -1392,7 +1403,7 @@ struct Smt2Backend : public Backend { log(" the given option as a `(set-option ...)` command in the SMT-LIBv2.\n"); log("\n"); log("[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David\n"); - log("R. Cok's tutorial: http://www.grammatech.com/resources/smt/SMTLIBTutorial.pdf\n"); + log("R. Cok's tutorial: https://smtlib.github.io/jSMTLIB/SMTLIBTutorial.pdf\n"); log("\n"); log("---------------------------------------------------------------------------\n"); log("\n"); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 19dd5af10..f4feed347 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3218,14 +3218,15 @@ skip_dynamic_range_lvalue_expansion:; if (wire_cache.count(child->str)) { wire = wire_cache.at(child->str); - if (wire->children.empty()) { + bool contains_value = wire->type == AST_LOCALPARAM; + if (wire->children.size() == contains_value) { for (auto c : child->children) wire->children.push_back(c->clone()); } else if (!child->children.empty()) { while (child->simplify(true, false, false, stage, -1, false, false)) { } - if (GetSize(child->children) == GetSize(wire->children)) { + if (GetSize(child->children) == GetSize(wire->children) - contains_value) { for (int i = 0; i < GetSize(child->children); i++) - if (*child->children.at(i) != *wire->children.at(i)) + if (*child->children.at(i) != *wire->children.at(i + contains_value)) goto tcall_incompatible_wires; } else { tcall_incompatible_wires: diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore deleted file mode 100644 index f586b33c7..000000000 --- a/frontends/ilang/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -ilang_lexer.cc -ilang_parser.output -ilang_parser.tab.cc -ilang_parser.tab.hh diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc deleted file mode 100644 index 6f1f0e8fc..000000000 --- a/frontends/ilang/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ - -GENFILES += frontends/ilang/ilang_parser.tab.cc -GENFILES += frontends/ilang/ilang_parser.tab.hh -GENFILES += frontends/ilang/ilang_parser.output -GENFILES += frontends/ilang/ilang_lexer.cc - -frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y - $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $< - -frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc - -frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l - $(Q) mkdir -p $(dir $@) - $(P) flex -o frontends/ilang/ilang_lexer.cc $< - -OBJS += frontends/ilang/ilang_parser.tab.o frontends/ilang/ilang_lexer.o -OBJS += frontends/ilang/ilang_frontend.o - diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 6d72cbff5..5a40001cb 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -378,7 +378,7 @@ struct RpcFrontend : public Pass { log(" -> {\"method\": \"derive\", \"module\": \"<module-name\">, \"parameters\": {\n"); log(" \"<param-name>\": {\"type\": \"[unsigned|signed|string|real]\",\n"); log(" \"value\": \"<param-value>\"}, ...}}\n"); - log(" <- {\"frontend\": \"[ilang|verilog|...]\",\"source\": \"<source>\"}}\n"); + log(" <- {\"frontend\": \"[rtlil|verilog|...]\",\"source\": \"<source>\"}}\n"); log(" <- {\"error\": \"<error-message>\"}\n"); log(" request for the module <module-name> to be derived for a specific set of\n"); log(" parameters. <param-name> starts with \\ for named parameters, and with $\n"); diff --git a/frontends/rtlil/.gitignore b/frontends/rtlil/.gitignore new file mode 100644 index 000000000..d4a322756 --- /dev/null +++ b/frontends/rtlil/.gitignore @@ -0,0 +1,4 @@ +rtlil_lexer.cc +rtlil_parser.output +rtlil_parser.tab.cc +rtlil_parser.tab.hh diff --git a/frontends/rtlil/Makefile.inc b/frontends/rtlil/Makefile.inc new file mode 100644 index 000000000..d0c0cfcf8 --- /dev/null +++ b/frontends/rtlil/Makefile.inc @@ -0,0 +1,19 @@ + +GENFILES += frontends/rtlil/rtlil_parser.tab.cc +GENFILES += frontends/rtlil/rtlil_parser.tab.hh +GENFILES += frontends/rtlil/rtlil_parser.output +GENFILES += frontends/rtlil/rtlil_lexer.cc + +frontends/rtlil/rtlil_parser.tab.cc: frontends/rtlil/rtlil_parser.y + $(Q) mkdir -p $(dir $@) + $(P) $(BISON) -o $@ -d -r all -b frontends/rtlil/rtlil_parser $< + +frontends/rtlil/rtlil_parser.tab.hh: frontends/rtlil/rtlil_parser.tab.cc + +frontends/rtlil/rtlil_lexer.cc: frontends/rtlil/rtlil_lexer.l + $(Q) mkdir -p $(dir $@) + $(P) flex -o frontends/rtlil/rtlil_lexer.cc $< + +OBJS += frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o +OBJS += frontends/rtlil/rtlil_frontend.o + diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 973e62f2c..00c34175e 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -18,30 +18,30 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ -#include "ilang_frontend.h" +#include "rtlil_frontend.h" #include "kernel/register.h" #include "kernel/log.h" -void rtlil_frontend_ilang_yyerror(char const *s) +void rtlil_frontend_yyerror(char const *s) { - YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s); + YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_yyget_lineno(), s); } YOSYS_NAMESPACE_BEGIN -struct IlangFrontend : public Frontend { - IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } +struct RTLILFrontend : public Frontend { + RTLILFrontend() : Frontend("rtlil", "read modules from RTLIL file") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" read_ilang [filename]\n"); + log(" read_rtlil [filename]\n"); log("\n"); - log("Load modules from an ilang file to the current design. (ilang is a text\n"); + log("Load modules from an RTLIL file to the current design. (RTLIL is a text\n"); log("representation of a design in yosys's internal format.)\n"); log("\n"); log(" -nooverwrite\n"); @@ -58,27 +58,27 @@ struct IlangFrontend : public Frontend { } void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override { - ILANG_FRONTEND::flag_nooverwrite = false; - ILANG_FRONTEND::flag_overwrite = false; - ILANG_FRONTEND::flag_lib = false; + RTLIL_FRONTEND::flag_nooverwrite = false; + RTLIL_FRONTEND::flag_overwrite = false; + RTLIL_FRONTEND::flag_lib = false; - log_header(design, "Executing ILANG frontend.\n"); + log_header(design, "Executing RTLIL frontend.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-nooverwrite") { - ILANG_FRONTEND::flag_nooverwrite = true; - ILANG_FRONTEND::flag_overwrite = false; + RTLIL_FRONTEND::flag_nooverwrite = true; + RTLIL_FRONTEND::flag_overwrite = false; continue; } if (arg == "-overwrite") { - ILANG_FRONTEND::flag_nooverwrite = false; - ILANG_FRONTEND::flag_overwrite = true; + RTLIL_FRONTEND::flag_nooverwrite = false; + RTLIL_FRONTEND::flag_overwrite = true; continue; } if (arg == "-lib") { - ILANG_FRONTEND::flag_lib = true; + RTLIL_FRONTEND::flag_lib = true; continue; } break; @@ -87,12 +87,27 @@ struct IlangFrontend : public Frontend { log("Input filename: %s\n", filename.c_str()); - ILANG_FRONTEND::lexin = f; - ILANG_FRONTEND::current_design = design; - rtlil_frontend_ilang_yydebug = false; - rtlil_frontend_ilang_yyrestart(NULL); - rtlil_frontend_ilang_yyparse(); - rtlil_frontend_ilang_yylex_destroy(); + RTLIL_FRONTEND::lexin = f; + RTLIL_FRONTEND::current_design = design; + rtlil_frontend_yydebug = false; + rtlil_frontend_yyrestart(NULL); + rtlil_frontend_yyparse(); + rtlil_frontend_yylex_destroy(); + } +} RTLILFrontend; + +struct IlangFrontend : public Frontend { + IlangFrontend() : Frontend("ilang", "(deprecated) alias of read_rtlil") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log("See `help read_rtlil`.\n"); + log("\n"); + } + void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override + { + RTLILFrontend.execute(f, filename, args, design); } } IlangFrontend; diff --git a/frontends/ilang/ilang_frontend.h b/frontends/rtlil/rtlil_frontend.h index f8a152841..a420778b0 100644 --- a/frontends/ilang/ilang_frontend.h +++ b/frontends/rtlil/rtlil_frontend.h @@ -18,18 +18,18 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ -#ifndef ILANG_FRONTEND_H -#define ILANG_FRONTEND_H +#ifndef RTLIL_FRONTEND_H +#define RTLIL_FRONTEND_H #include "kernel/yosys.h" YOSYS_NAMESPACE_BEGIN -namespace ILANG_FRONTEND { +namespace RTLIL_FRONTEND { extern std::istream *lexin; extern RTLIL::Design *current_design; extern bool flag_nooverwrite; @@ -39,13 +39,13 @@ namespace ILANG_FRONTEND { YOSYS_NAMESPACE_END -extern int rtlil_frontend_ilang_yydebug; -int rtlil_frontend_ilang_yylex(void); -void rtlil_frontend_ilang_yyerror(char const *s); -void rtlil_frontend_ilang_yyrestart(FILE *f); -int rtlil_frontend_ilang_yyparse(void); -int rtlil_frontend_ilang_yylex_destroy(void); -int rtlil_frontend_ilang_yyget_lineno(void); +extern int rtlil_frontend_yydebug; +int rtlil_frontend_yylex(void); +void rtlil_frontend_yyerror(char const *s); +void rtlil_frontend_yyrestart(FILE *f); +int rtlil_frontend_yyparse(void); +int rtlil_frontend_yylex_destroy(void); +int rtlil_frontend_yyget_lineno(void); #endif diff --git a/frontends/ilang/ilang_lexer.l b/frontends/rtlil/rtlil_lexer.l index 3362ed641..295455f53 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/rtlil/rtlil_lexer.l @@ -18,7 +18,7 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ @@ -30,20 +30,20 @@ #endif #include <cstdlib> -#include "frontends/ilang/ilang_frontend.h" -#include "ilang_parser.tab.hh" +#include "frontends/rtlil/rtlil_frontend.h" +#include "rtlil_parser.tab.hh" USING_YOSYS_NAMESPACE #define YY_INPUT(buf,result,max_size) \ - result = readsome(*ILANG_FRONTEND::lexin, buf, max_size) + result = readsome(*RTLIL_FRONTEND::lexin, buf, max_size) %} %option yylineno %option noyywrap %option nounput -%option prefix="rtlil_frontend_ilang_yy" +%option prefix="rtlil_frontend_yy" %x STRING @@ -84,11 +84,11 @@ USING_YOSYS_NAMESPACE [a-z]+ { return TOK_INVALID; } -"\\"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"$"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } -"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; } +"\\"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } +"$"[^ \t\r\n]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } +"."[0-9]+ { rtlil_frontend_yylval.string = strdup(yytext); return TOK_ID; } -[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; } +[0-9]+'[01xzm-]* { rtlil_frontend_yylval.string = strdup(yytext); return TOK_VALUE; } -?[0-9]+ { char *end = nullptr; errno = 0; @@ -98,7 +98,7 @@ USING_YOSYS_NAMESPACE return TOK_INVALID; // literal out of range of long if (value < INT_MIN || value > INT_MAX) return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms) - rtlil_frontend_ilang_yylval.integer = value; + rtlil_frontend_yylval.integer = value; return TOK_INT; } @@ -131,7 +131,7 @@ USING_YOSYS_NAMESPACE yystr[j++] = yystr[i++]; } yystr[j] = 0; - rtlil_frontend_ilang_yylval.string = yystr; + rtlil_frontend_yylval.string = yystr; return TOK_STRING; } <STRING>. { yymore(); } @@ -145,6 +145,6 @@ USING_YOSYS_NAMESPACE %% // this is a hack to avoid the 'yyinput defined but not used' error msgs -void *rtlil_frontend_ilang_avoid_input_warnings() { +void *rtlil_frontend_avoid_input_warnings() { return (void*)&yyinput; } diff --git a/frontends/ilang/ilang_parser.y b/frontends/rtlil/rtlil_parser.y index 879ef4af9..646489196 100644 --- a/frontends/ilang/ilang_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -18,15 +18,15 @@ * --- * * A very simple and straightforward frontend for the RTLIL text - * representation (as generated by the 'ilang' backend). + * representation. * */ %{ #include <list> -#include "frontends/ilang/ilang_frontend.h" +#include "frontends/rtlil/rtlil_frontend.h" YOSYS_NAMESPACE_BEGIN -namespace ILANG_FRONTEND { +namespace RTLIL_FRONTEND { std::istream *lexin; RTLIL::Design *current_design; RTLIL::Module *current_module; @@ -40,12 +40,12 @@ namespace ILANG_FRONTEND { bool flag_nooverwrite, flag_overwrite, flag_lib; bool delete_current_module; } -using namespace ILANG_FRONTEND; +using namespace RTLIL_FRONTEND; YOSYS_NAMESPACE_END USING_YOSYS_NAMESPACE %} -%define api.prefix {rtlil_frontend_ilang_yy} +%define api.prefix {rtlil_frontend_yy} /* The union is defined in the header, so we need to provide all the * includes it requires @@ -53,7 +53,7 @@ USING_YOSYS_NAMESPACE %code requires { #include <string> #include <vector> -#include "frontends/ilang/ilang_frontend.h" +#include "frontends/rtlil/rtlil_frontend.h" } %union { @@ -87,7 +87,7 @@ input: attrbuf.clear(); } design { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); }; EOL: @@ -111,7 +111,7 @@ module: log("Ignoring blackbox re-definition of module %s.\n", $2); delete_current_module = true; } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of module %s.", $2).c_str()); } else if (flag_nooverwrite) { log("Ignoring re-definition of module %s.\n", $2); delete_current_module = true; @@ -129,7 +129,7 @@ module: free($2); } module_body TOK_END { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); current_module->fixup_ports(); if (delete_current_module) delete current_module; @@ -172,12 +172,12 @@ autoidx_stmt: wire_stmt: TOK_WIRE { - current_wire = current_module->addWire("$__ilang_frontend_tmp__"); + current_wire = current_module->addWire("$__rtlil_frontend_tmp__"); current_wire->attributes = attrbuf; attrbuf.clear(); } wire_options TOK_ID EOL { if (current_module->wire($4) != nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of wire %s.", $4).c_str()); current_module->rename(current_wire, $4); free($4); }; @@ -187,7 +187,7 @@ wire_options: current_wire->width = $3; } | wire_options TOK_WIDTH TOK_INVALID { - rtlil_frontend_ilang_yyerror("ilang error: invalid wire width"); + rtlil_frontend_yyerror("RTLIL error: invalid wire width"); } | wire_options TOK_UPTO { current_wire->upto = true; @@ -222,7 +222,7 @@ memory_stmt: attrbuf.clear(); } memory_options TOK_ID EOL { if (current_module->memories.count($4) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of memory %s.", $4).c_str()); current_memory->name = $4; current_module->memories[$4] = current_memory; free($4); @@ -243,7 +243,7 @@ memory_options: cell_stmt: TOK_CELL TOK_ID TOK_ID EOL { if (current_module->cell($3) != nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of cell %s.", $3).c_str()); current_cell = current_module->addCell($3, $2); current_cell->attributes = attrbuf; attrbuf.clear(); @@ -271,7 +271,7 @@ cell_body: } | cell_body TOK_CONNECT TOK_ID sigspec EOL { if (current_cell->hasPort($3)) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of cell port %s.", $3).c_str()); current_cell->setPort($3, *$4); delete $4; free($3); @@ -281,7 +281,7 @@ cell_body: proc_stmt: TOK_PROCESS TOK_ID EOL { if (current_module->processes.count($2) != 0) - rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: redefinition of process %s.", $2).c_str()); current_process = new RTLIL::Process; current_process->name = $2; current_process->attributes = attrbuf; @@ -342,7 +342,7 @@ case_body: assign_stmt: TOK_ASSIGN sigspec sigspec EOL { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3)); delete $2; delete $3; @@ -438,19 +438,19 @@ sigspec: } | TOK_ID { if (current_module->wire($1) == nullptr) - rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str()); + rtlil_frontend_yyerror(stringf("RTLIL error: wire %s not found", $1).c_str()); $$ = new RTLIL::SigSpec(current_module->wire($1)); free($1); } | sigspec '[' TOK_INT ']' { if ($3 >= $1->size() || $3 < 0) - rtlil_frontend_ilang_yyerror("bit index out of range"); + rtlil_frontend_yyerror("bit index out of range"); $$ = new RTLIL::SigSpec($1->extract($3)); delete $1; } | sigspec '[' TOK_INT ':' TOK_INT ']' { if ($3 >= $1->size() || $3 < 0 || $3 < $5) - rtlil_frontend_ilang_yyerror("invalid slice"); + rtlil_frontend_yyerror("invalid slice"); $$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1)); delete $1; } | @@ -477,7 +477,7 @@ sigspec_list: sigspec_list_reversed { conn_stmt: TOK_CONNECT sigspec sigspec EOL { if (attrbuf.size() != 0) - rtlil_frontend_ilang_yyerror("dangling attribute"); + rtlil_frontend_yyerror("dangling attribute"); current_module->connect(*$2, *$3); delete $2; delete $3; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 632dc51fd..40dca20ba 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -54,7 +54,7 @@ USING_YOSYS_NAMESPACE # error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." #endif -#if SYMBIOTIC_VERIFIC_API_VERSION < 202006 +#if SYMBIOTIC_VERIFIC_API_VERSION < 20200702 # error "Please update your version of Symbiotic EDA flavored Verific." #endif @@ -199,12 +199,17 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k)); } else if (nl->IsFromVhdl()) { - // Expect "<binary>" + // Expect "<binary>" or plain <binary> auto p = v; if (p) { - if (*p != '"') - p = nullptr; - else { + if (*p != '"') { + auto l = strlen(p); + auto q = (char*)malloc(l+1); + strncpy(q, p, l); + q[l] = '\0'; + for(char *ptr = q; *ptr; ++ptr )*ptr = tolower(*ptr); + attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); + } else { auto *q = p+1; for (; *q != '"'; q++) if (*q != '0' && *q != '1') { @@ -213,16 +218,20 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att } if (p && *(q+1) != '\0') p = nullptr; + + if (p != nullptr) + { + auto l = strlen(p); + auto q = (char*)malloc(l+1-2); + strncpy(q, p+1, l-2); + q[l-2] = '\0'; + attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); + free(q); + } } } if (p == nullptr) - log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v); - auto l = strlen(p); - auto q = (char*)malloc(l+1-2); - strncpy(q, p+1, l-2); - q[l-2] = '\0'; - attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k)); - free(q); + log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v); } } } @@ -2158,6 +2167,70 @@ struct VerificPass : public Pass { log(" Dump the Verific netlist as a verilog file.\n"); log("\n"); log("\n"); + log(" verific [-work <libname>] -pp [options] <filename> [<module>]..\n"); + log("\n"); + log("Pretty print design (or just module) to the specified file from the\n"); + log("specified library. (default library when -work is not present: \"work\")\n"); + log("\n"); + log("Pretty print options:\n"); + log("\n"); + log(" -verilog\n"); + log(" Save output for Verilog/SystemVerilog design modules (default).\n"); + log("\n"); + log(" -vhdl\n"); + log(" Save output for VHDL design units.\n"); + log("\n"); + log("\n"); + log(" verific -app <application>..\n"); + log("\n"); + log("Execute SEDA formal application on loaded Verilog files.\n"); + log("\n"); + log("Application options:\n"); + log("\n"); + log(" -blacklist <filename[:lineno]>\n"); + log(" Do not run application on modules from files that match the filename\n"); + log(" or filename and line number if provided in such format.\n"); + log(" Parameter can also contain comma separated list of file locations.\n"); + log("\n"); + log(" -blfile <file>\n"); + log(" Do not run application on locations specified in file, they can represent filename\n"); + log(" or filename and location in file.\n"); + log("\n"); + log("Applications:\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + VerificFormalApplications vfa; + log("%s\n",vfa.GetHelp().c_str()); +#else + log(" WARNING: Applications only available in commercial build.\n"); + +#endif + log("\n"); + log("\n"); + log(" verific -template <name> <top_module>..\n"); + log("\n"); + log("Generate template for specified top module of loaded design.\n"); + log("\n"); + log("Template options:\n"); + log("\n"); + log(" -out\n"); + log(" Specifies output file for generated template, by default output is stdout\n"); + log("\n"); + log(" -chparam name value \n"); + log(" Generate template using this parameter value. Otherwise default parameter\n"); + log(" values will be used for templat generate functionality. This option\n"); + log(" can be specified multiple times to override multiple parameters.\n"); + log(" String values must be passed in double quotes (\").\n"); + log("\n"); + log("Templates:\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + VerificTemplateGenerator vfg; + log("%s\n",vfg.GetHelp().c_str()); +#else + log(" WARNING: Templates only available in commercial build.\n"); + log("\n"); +#endif log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"); log("https://www.symbioticeda.com/seda-suite\n"); log("\n"); @@ -2202,6 +2275,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_preserve_assignments", 1); RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); + RuntimeFlags::SetVar("veri_preserve_comments",1); + //RuntimeFlags::SetVar("vhdl_preserve_comments",1); + // Workaround for VIPER #13851 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); @@ -2399,6 +2475,161 @@ struct VerificPass : public Pass { goto check_error; } + if (argidx+1 < GetSize(args) && args[argidx] == "-app") + { + VerificFormalApplications vfa; + auto apps = vfa.GetApps(); + std::string app = args[++argidx]; + std::vector<std::string> blacklists; + if (apps.find(app) == apps.end()) + log_cmd_error("Application '%s' does not exist.\n", app.c_str()); + + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-blacklist" && argidx+1 < GetSize(args)) { + std::string line = args[++argidx]; + std::string p; + while (!(p = next_token(line, ",\t\r\n ")).empty()) + blacklists.push_back(p); + continue; + } + if (args[argidx] == "-blfile" && argidx+1 < GetSize(args)) { + std::string fn = args[++argidx]; + std::ifstream f(fn); + if (f.fail()) + log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str()); + + std::string line,p; + while (std::getline(f, line)) { + while (!(p = next_token(line, ",\t\r\n ")).empty()) + blacklists.push_back(p); + } + continue; + } + break; + } + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + MapIter mi; + VeriModule *module ; + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); + log("Running formal application '%s'.\n", app.c_str()); + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, module) { + vfa.Run(module,apps[app],blacklists); + } + goto check_error; + } + + if (argidx < GetSize(args) && args[argidx] == "-pp") + { + const char* filename = nullptr; + const char* module = nullptr; + bool mode_vhdl = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-vhdl") { + mode_vhdl = true; + continue; + } + if (args[argidx] == "-verilog") { + mode_vhdl = false; + continue; + } + + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + + if (!filename) { + filename = args[argidx].c_str(); + continue; + } + if (module) + log_cmd_error("Only one module can be specified.\n"); + module = args[argidx].c_str(); + } + + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + + if (!filename) + log_cmd_error("Filname must be specified.\n"); + + if (mode_vhdl) + vhdl_file::PrettyPrint(filename, module, work.c_str()); + else + veri_file::PrettyPrint(filename, module, work.c_str()); + goto check_error; + } + + if (argidx < GetSize(args) && args[argidx] == "-template") + { + if (!(argidx < GetSize(args))) + cmd_error(args, argidx, "No template type specified.\n"); + + VerificTemplateGenerator vfg; + auto gens = vfg.GetGenerators(); + std::string app = args[++argidx]; + if (gens.find(app) == gens.end()) + log_cmd_error("Template generator '%s' does not exist.\n", app.c_str()); + TemplateGenerator *generator = gens[app]; + if (!(argidx < GetSize(args))) + cmd_error(args, argidx, "No top module specified.\n"); + + std::string module = args[++argidx]; + VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); + VeriModule *veri_module = veri_lib ? veri_lib->GetModule(module.c_str(), 1) : nullptr; + if (!veri_module) { + log_error("Can't find module/unit '%s'.\n", module.c_str()); + } + + log("Template '%s' is running for module '%s'.\n", app.c_str(),module.c_str()); + + Map parameters(STRING_HASH); + const char *out_filename = nullptr; + + for (argidx++; argidx < GetSize(args); argidx++) { + if (generator->checkParams(args, argidx)) + continue; + if (args[argidx] == "-chparam" && argidx+2 < GetSize(args)) { + const std::string &key = args[++argidx]; + const std::string &value = args[++argidx]; + unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(), + 1 /* force_overwrite */); + if (!new_insertion) + log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str()); + continue; + } + + if (args[argidx] == "-out" && argidx+1 < GetSize(args)) { + out_filename = args[++argidx].c_str(); + continue; + } + + break; + } + if (argidx < GetSize(args)) + cmd_error(args, argidx, "unknown option/parameter"); + + const char *err = generator->validate(); + if (err) + cmd_error(args, argidx, err); + + std::string val = generator->generate(veri_module, ¶meters); + + FILE *of = stdout; + if (out_filename) { + of = fopen(out_filename, "w"); + if (of == nullptr) + log_error("Can't open '%s' for writing: %s\n", out_filename, strerror(errno)); + log("Writing output to '%s'\n",out_filename); + } + fprintf(of, "%s\n",val.c_str()); + fflush(of); + if (of!=stdout) + fclose(of); + goto check_error; + } + if (GetSize(args) > argidx && args[argidx] == "-import") { std::set<Netlist*> nl_todo, nl_done; diff --git a/kernel/log.cc b/kernel/log.cc index 1c1d0182e..c7ae873bc 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -19,7 +19,7 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" #if !defined(_WIN32) || defined(__MINGW32__) # include <sys/time.h> @@ -600,7 +600,7 @@ void log_dump_val_worker(RTLIL::State v) { const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) { std::stringstream buf; - ILANG_BACKEND::dump_sigspec(buf, sig, autoint); + RTLIL_BACKEND::dump_sigspec(buf, sig, autoint); if (string_buf.size() < 100) { string_buf.push_back(buf.str()); @@ -647,21 +647,21 @@ const char *log_id(RTLIL::IdString str) void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_module(buf, indent, module, module->design, false); + RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false); log("%s", buf.str().c_str()); } void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_cell(buf, indent, cell); + RTLIL_BACKEND::dump_cell(buf, indent, cell); log("%s", buf.str().c_str()); } void log_wire(RTLIL::Wire *wire, std::string indent) { std::stringstream buf; - ILANG_BACKEND::dump_wire(buf, indent, wire); + RTLIL_BACKEND::dump_wire(buf, indent, wire); log("%s", buf.str().c_str()); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c56f0dcab..a9f585616 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -22,7 +22,7 @@ #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/verilog/preproc.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" #include <string.h> #include <algorithm> @@ -923,7 +923,7 @@ namespace { void error(int linenr) { std::stringstream buf; - ILANG_BACKEND::dump_cell(buf, " ", cell); + RTLIL_BACKEND::dump_cell(buf, " ", cell); log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", module ? module->name.c_str() : "", module ? "." : "", diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8986c8091..7a2ef4913 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -930,7 +930,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-5, std::string::npos, ".json") == 0) command = "json"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".il") == 0) - command = "ilang"; + command = "rtlil"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".ys") == 0) command = "script"; else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".tcl") == 0) @@ -1053,7 +1053,7 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".sv") == 0) command = "verilog -sv"; else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0) - command = "ilang"; + command = "rtlil"; else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".cc") == 0) command = "cxxrtl"; else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0) @@ -1065,7 +1065,7 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".json") == 0) command = "json"; else if (filename == "-") - command = "ilang"; + command = "rtlil"; else if (filename.empty()) return; else diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 83cfa5cc4..ed8b4cd49 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -39,15 +39,15 @@ the RTL Intermediate Language (RTLIL). A more detailed description of this forma is given in the next section. There is also a text representation of the RTLIL data structure that can be -parsed using the ILANG Frontend. +parsed using the RTLIL Frontend. The design data may then be transformed using a series of passes that all operate on the RTLIL representation of the design. Finally the design in RTLIL representation is converted back to text by one of the backends, namely the Verilog Backend for generating Verilog netlists -and the ILANG Backend for writing the RTLIL data in the same format that is -understood by the ILANG Frontend. +and the RTLIL Backend for writing the RTLIL data in the same format that is +understood by the RTLIL Frontend. With the exception of the AST Frontend, which is called by the high-level HDL frontends and can't be called directly by the user, all program modules are @@ -67,13 +67,13 @@ in different stages of the synthesis. \tikzstyle{data} = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em] \node[process] (vlog) {Verilog Frontend}; \node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend}; - \node[process] (ilang) [right of=vhdl] {ILANG Frontend}; + \node[process] (ilang) [right of=vhdl] {RTLIL Frontend}; \node[data] (ast) [below of=vlog, node distance=5em, xshift=7.5em] {AST}; \node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend}; \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -92,8 +92,7 @@ in different stages of the synthesis. \section{The RTL Intermediate Language} -All frontends, passes and backends in Yosys operate on a design in RTLIL\footnote{The {\it Language} in {\it RTL Intermediate Language} -refers to the fact, that RTLIL also has a text representation, usually referred to as {\it Intermediate Language} (ILANG).} representation. +All frontends, passes and backends in Yosys operate on a design in RTLIL representation. The only exception are the high-level frontends that use the AST representation as an intermediate step before generating RTLIL data. @@ -316,7 +315,7 @@ endmodule In this example there is no data path and therefore the RTLIL::Module generated by the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process. -The RTLIL::Process in ILANG syntax: +The RTLIL::Process in RTLIL syntax: \begin{lstlisting}[numbers=left,frame=single,language=rtlil] process $proc$ff_with_en_and_async_reset.v:4$1 @@ -362,7 +361,7 @@ also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object i statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine which of its cases should be active. The RTLIL::SwitchRule object then contains one RTLIL::CaseRule object per case. In this example there is a case\footnote{The -syntax {\tt 1'1} in the ILANG code specifies a constant with a length of one bit (the first ``1''), +syntax {\tt 1'1} in the RTLIL code specifies a constant with a length of one bit (the first ``1''), and this bit is a one (the second ``1'').} for {\tt \textbackslash{}reset == 1} that causes {\tt \$0\textbackslash{}q[0:0]} to be set (lines 4 and 5) and a default case that in turn contains a switch that sets {\tt \$0\textbackslash{}q[0:0]} to the value of {\tt \textbackslash{}d} if {\tt diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 555ec9175..af561d01b 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -231,7 +231,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -484,7 +484,7 @@ Commands for design navigation and investigation: \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] cd # a shortcut for 'select -module <name>' ls # list modules or objects in modules - dump # print parts of the design in ilang format + dump # print parts of the design in RTLIL format show # generate schematics using graphviz select # modify and view the list of selected objects \end{lstlisting} @@ -502,7 +502,7 @@ Commands for executing scripts or entering interactive mode: \begin{frame}[fragile]{\subsecname{} 2/3 \hspace{0pt plus 1 filll} (excerpt)} Commands for reading and elaborating the design: \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys] - read_ilang # read modules from ilang file + read_rtlil # read modules from RTLIL file read_verilog # read modules from Verilog file hierarchy # check, expand and clean up design hierarchy \end{lstlisting} @@ -534,7 +534,7 @@ Commands for writing the results: write_blif # write design to BLIF file write_btor # write design to BTOR file write_edif # write design to EDIF netlist file - write_ilang # write design to ilang file + write_rtlil # write design to RTLIL file write_spice # write design to SPICE netlist file write_verilog # write design to Verilog file \end{lstlisting} diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index a9416f82a..3b61361af 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -22,7 +22,7 @@ \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -105,8 +105,7 @@ For simplicity we only discuss this version of RTLIL in this presentation. \begin{frame}{\subsecname} \begin{itemize} -\item The {\tt dump} command prints the design (or parts of it) in ILANG format. This is -a text representation of RTLIL. +\item The {\tt dump} command prints the design (or parts of it) in the text representation of RTLIL. \bigskip \item The {\tt show} command visualizes how the components in the design are connected. diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 98d42aa83..81d7a34bb 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -18,10 +18,10 @@ */ #include "kernel/yosys.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" USING_YOSYS_NAMESPACE -using namespace ILANG_BACKEND; +using namespace RTLIL_BACKEND; PRIVATE_NAMESPACE_BEGIN struct BugpointPass : public Pass { @@ -90,7 +90,7 @@ struct BugpointPass : public Pass { design->sort(); std::ofstream f("bugpoint-case.il"); - ILANG_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); + RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); f.close(); string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str()); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index cbed08a3f..a4ad861f6 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -605,7 +605,7 @@ struct ShowPass : public Pass { log(" generate a .dot file, or other <format> strings such as 'svg' or 'ps'\n"); log(" to generate files in other formats (this calls the 'dot' command).\n"); log("\n"); - log(" -lib <verilog_or_ilang_file>\n"); + log(" -lib <verilog_or_rtlil_file>\n"); log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); @@ -811,7 +811,7 @@ struct ShowPass : public Pass { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a2a428d15..90b25949d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -224,7 +224,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { {".v", "verilog"}, {".sv", "verilog -sv"}, - {".il", "ilang"} + {".il", "rtlil"} }; for (auto &ext : extensions_list) diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index f20a167b4..09cf0af82 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -50,6 +50,9 @@ struct ProcPass : public Pass { log("\n"); log("The following options are supported:\n"); log("\n"); + log(" -nomux\n"); + log(" Will omit the proc_mux pass.\n"); + log("\n"); log(" -global_arst [!]<netname>\n"); log(" This option is passed through to proc_arst.\n"); log("\n"); @@ -62,6 +65,7 @@ struct ProcPass : public Pass { { std::string global_arst; bool ifxmode = false; + bool nomux = false; log_header(design, "Executing PROC pass (convert processes to netlists).\n"); log_push(); @@ -69,6 +73,10 @@ struct ProcPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } if (args[argidx] == "-global_arst" && argidx+1 < args.size()) { global_arst = args[++argidx]; continue; @@ -90,7 +98,8 @@ struct ProcPass : public Pass { Pass::call(design, "proc_arst"); else Pass::call(design, "proc_arst -global_arst " + global_arst); - Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); + if (!nomux) + Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); Pass::call(design, "proc_dlatch"); Pass::call(design, "proc_dff"); Pass::call(design, "proc_clean"); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 8ad65493f..c1e7e557d 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -418,7 +418,8 @@ unmap_enable: ff_type = has_set ? FF_ADFFE1 : FF_ADFFE0; break; } - if (supported_dffsr & initmask) { + if (supported_cells[has_en ? FF_DFFSRE : FF_DFFSR] & initmask) { +adff_to_dffsr: // Throw in a set/reset, retry in DFFSR/DFFSRE branch. if (has_set) { sig_s = sig_r; @@ -441,6 +442,9 @@ unmap_enable: ff_type = has_set ? FF_ADFF1 : FF_ADFF0; goto unmap_enable; } + if (supported_dffsr & initmask) { + goto adff_to_dffsr; + } log_assert(!((has_set ? supported_adff1 : supported_adff0) & initmask)); // Alright, so this particular combination of initval and // resetval is not natively supported. First, try flipping diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 7278cb680..f5966fac0 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -354,7 +354,7 @@ struct ExtractPass : public Pass { log("\n"); log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); log("in the given map file and replaces them with instances of this modules. The\n"); - log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n"); + log("map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).\n"); log("\n"); log(" -map <map_file>\n"); log(" use the modules in this file as reference. This option can be used\n"); @@ -409,7 +409,7 @@ struct ExtractPass : public Pass { log("the following options are to be used instead of the -map option.\n"); log("\n"); log(" -mine <out_file>\n"); - log(" mine for frequent subcircuits and write them to the given ilang file\n"); + log(" mine for frequent subcircuits and write them to the given RTLIL file\n"); log("\n"); log(" -mine_cells_span <min> <max>\n"); log(" only mine for subcircuits with the specified number of cells\n"); @@ -578,7 +578,7 @@ struct ExtractPass : public Pass { } if (map_filenames.empty() && mine_outfile.empty()) - log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n"); + log_cmd_error("Missing option -map <verilog_or_rtlil_file> or -mine <output_rtlil_file>.\n"); RTLIL::Design *map = nullptr; @@ -606,7 +606,7 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); } - Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); + Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); f.close(); if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) { @@ -744,7 +744,7 @@ struct ExtractPass : public Pass { f.open(mine_outfile.c_str(), std::ofstream::trunc); if (f.fail()) log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); - Backend::backend_call(map, &f, mine_outfile, "ilang"); + Backend::backend_call(map, &f, mine_outfile, "rtlil"); f.close(); } diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index b5f55cffa..08978f446 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -152,15 +152,14 @@ struct FlattenWorker // Attach port connections of the flattened cell - SigMap tpl_sigmap(tpl); pool<SigBit> tpl_driven; for (auto tpl_cell : tpl->cells()) for (auto &tpl_conn : tpl_cell->connections()) if (tpl_cell->output(tpl_conn.first)) - for (auto bit : tpl_sigmap(tpl_conn.second)) + for (auto bit : tpl_conn.second) tpl_driven.insert(bit); for (auto &tpl_conn : tpl->connections()) - for (auto bit : tpl_sigmap(tpl_conn.first)) + for (auto bit : tpl_conn.first) tpl_driven.insert(bit); SigMap sigmap(module); @@ -190,7 +189,7 @@ struct FlattenWorker } else { SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { - if (tpl_driven.count(tpl_sigmap(sig_tpl[i]))) { + if (tpl_driven.count(sig_tpl[i])) { new_conn.first.append(sig_mod[i]); new_conn.second.append(sig_tpl[i]); } else { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4a1a74ce9..d43737c8d 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -233,16 +233,14 @@ struct TechmapWorker } } - SigMap tpl_sigmap(tpl); pool<SigBit> tpl_written_bits; - for (auto tpl_cell : tpl->cells()) for (auto &conn : tpl_cell->connections()) if (tpl_cell->output(conn.first)) - for (auto bit : tpl_sigmap(conn.second)) + for (auto bit : conn.second) tpl_written_bits.insert(bit); for (auto &conn : tpl->connections()) - for (auto bit : tpl_sigmap(conn.first)) + for (auto bit : conn.first) tpl_written_bits.insert(bit); SigMap port_signal_map; @@ -280,7 +278,7 @@ struct TechmapWorker SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second; apply_prefix(cell->name, sig_tpl_pf, module); for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { - if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) { + if (tpl_written_bits.count(sig_tpl[i])) { c.first.append(sig_mod[i]); c.second.append(sig_tpl_pf[i]); } else { @@ -985,7 +983,7 @@ struct TechmapPass : public Pass { log(" techmap [-map filename] [selection]\n"); log("\n"); log("This pass implements a very simple technology mapper that replaces cells in\n"); - log("the design with implementations given in form of a Verilog or ilang source\n"); + log("the design with implementations given in form of a Verilog or RTLIL source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); @@ -1212,7 +1210,7 @@ struct TechmapPass : public Pass { if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 2d80e66e4..ac31e36f1 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -171,7 +171,7 @@ static void test_abcloop() } log("Found viable UUT after %d cycles:\n", create_cycles); - Pass::call(design, "write_ilang"); + Pass::call(design, "write_rtlil"); Pass::call(design, "abc"); log("\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 228b6b67a..616981f32 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -678,12 +678,12 @@ struct TestCellPass : public Pass { log(" -s {positive_integer}\n"); log(" use this value as rng seed value (default = unix time).\n"); log("\n"); - log(" -f {ilang_file}\n"); - log(" don't generate circuits. instead load the specified ilang file.\n"); + log(" -f {rtlil_file}\n"); + log(" don't generate circuits. instead load the specified RTLIL file.\n"); log("\n"); log(" -w {filename_prefix}\n"); log(" don't test anything. just generate the circuits and write them\n"); - log(" to ilang files with the specified prefix\n"); + log(" to RTLIL files with the specified prefix\n"); log("\n"); log(" -map {filename}\n"); log(" pass this option to techmap.\n"); @@ -724,7 +724,7 @@ struct TestCellPass : public Pass { { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; - std::string ilang_file, write_prefix; + std::string rtlil_file, write_prefix; xorshift32_state = 0; std::ofstream vlog_file; bool muxdiv = false; @@ -750,7 +750,7 @@ struct TestCellPass : public Pass { continue; } if (args[argidx] == "-f" && argidx+1 < GetSize(args)) { - ilang_file = args[++argidx]; + rtlil_file = args[++argidx]; num_iter = 1; continue; } @@ -910,10 +910,10 @@ struct TestCellPass : public Pass { selected_cell_types.push_back(args[argidx]); } - if (!ilang_file.empty()) { + if (!rtlil_file.empty()) { if (!selected_cell_types.empty()) log_cmd_error("Do not specify any cell types when using -f.\n"); - selected_cell_types.push_back(ID(ilang)); + selected_cell_types.push_back(ID(rtlil)); } if (selected_cell_types.empty()) @@ -925,12 +925,12 @@ struct TestCellPass : public Pass { for (int i = 0; i < num_iter; i++) { RTLIL::Design *design = new RTLIL::Design; - if (cell_type == ID(ilang)) - Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); + if (cell_type == ID(rtlil)) + Frontend::frontend_call(design, NULL, std::string(), "rtlil " + rtlil_file); else create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); if (!write_prefix.empty()) { - Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); + Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); } else if (edges) { Pass::call(design, "dump gold"); run_edges_test(design, verbose); diff --git a/techlibs/intel_alm/common/dsp_map.v b/techlibs/intel_alm/common/dsp_map.v index d1bc25e65..e12e777a4 100644 --- a/techlibs/intel_alm/common/dsp_map.v +++ b/techlibs/intel_alm/common/dsp_map.v @@ -1,3 +1,5 @@ +`default_nettype none + module __MUL27X27(A, B, Y); parameter A_SIGNED = 1; diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index 45fdebb3f..bdb6d18d5 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,38 +1,83 @@ (* abc9_box *) module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 3732; (B *> Y) = 3928; endspecify -assign Y = $signed(A) * $signed(B); +wire [53:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 3180; (B *> Y) = 3982; endspecify -assign Y = $signed(A) * $signed(B); +wire [35:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule (* abc9_box *) module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + // TODO: Cyclone 10 GX timings; the below are for Cyclone V specify (A *> Y) = 2818; (B *> Y) = 3051; endspecify -assign Y = $signed(A) * $signed(B); +wire [17:0] A_, B_; + +if (A_SIGNED) + assign A_ = $signed(A); +else + assign A_ = $unsigned(A); + +if (B_SIGNED) + assign B_ = $signed(B); +else + assign B_ = $unsigned(B); + +assign Y = A_ * B_; endmodule diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v index 530e44054..874f293b1 100644 --- a/techlibs/intel_alm/common/megafunction_bb.v +++ b/techlibs/intel_alm/common/megafunction_bb.v @@ -565,7 +565,9 @@ endmodule module cyclonev_mac(ax, ay, resulta); parameter ax_width = 9; +parameter signed_max = "true"; parameter ay_scan_in_width = 9; +parameter signed_may = "true"; parameter result_a_width = 18; parameter operation_mode = "M9x9"; @@ -579,7 +581,9 @@ endmodule module cyclone10gx_mac(ax, ay, resulta); parameter ax_width = 18; +parameter signed_max = "true"; parameter ay_scan_in_width = 18; +parameter signed_may = "true"; parameter result_a_width = 36; parameter operation_mode = "M18X18_FULL"; diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 9bc532ca2..3b4628675 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -174,20 +174,62 @@ endmodule module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y); -`MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(27), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(27), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(54), + .operation_mode("M27x27") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y); -`MAC #(.ax_width(18), .ay_scan_in_width(18), .result_a_width(36), .operation_mode("M18x18_FULL")) _TECHMAP_REPLACE_ (.ax(B), .ay(A), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(18), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(18), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(36), + .operation_mode("M18x18_FULL") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y); -`MAC #(.ax_width(9), .ay_scan_in_width(9), .result_a_width(18), .operation_mode("M9x9")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); +parameter A_SIGNED = 1; +parameter B_SIGNED = 1; + +`MAC #( + .ax_width(9), + .signed_max(A_SIGNED ? "true" : "false"), + .ay_scan_in_width(9), + .signed_may(B_SIGNED ? "true" : "false"), + .result_a_width(18), + .operation_mode("M9x9") +) _TECHMAP_REPLACE_ ( + .ax(A), + .ay(B), + .resulta(Y) +); endmodule diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 7ab50ef8f..6719eb65c 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -214,15 +214,19 @@ struct SynthIntelALMPass : public ScriptPass { run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)"); } else if (!nodsp) { // Cyclone V supports 9x9 multiplication, Cyclone 10 GX does not. - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=19 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL27X27"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL27X27"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=19 -D DSP_NAME=__MUL27X27"); run("chtype -set $mul t:$__soft_mul"); if (family_opt == "cyclonev") { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=__MUL18X18"); run("chtype -set $mul t:$__soft_mul"); - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL9X9"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL9X9"); run("chtype -set $mul t:$__soft_mul"); } else if (family_opt == "cyclone10gx") { - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=__MUL18X18"); run("chtype -set $mul t:$__soft_mul"); } } diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index 437a91cfc..baed64fcd 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,9 +1,10 @@ module top +#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12) ( - input [5:0] x, - input [5:0] y, + input [X_WIDTH-1:0] x, + input [Y_WIDTH-1:0] y, - output [11:0] A, + output [A_WIDTH-1:0] A, ); assign A = x * y; endmodule diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys index 92f00156a..49934740f 100644 --- a/tests/arch/intel_alm/mul.ys +++ b/tests/arch/intel_alm/mul.ys @@ -1,23 +1,60 @@ read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat - select -assert-count 1 t:MISTRAL_MUL9X9 select -assert-none t:MISTRAL_MUL9X9 %% t:* %D +# Cyclone 10 GX does not have 9x9 multipliers. + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL18X18 +select -assert-none t:MISTRAL_MUL18X18 %% t:* %D + design -reset read_verilog ../common/mul.v +chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18. select -assert-count 1 t:MISTRAL_MUL18X18 select -assert-none t:MISTRAL_MUL18X18 %% t:* %D + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL27X27 +select -assert-none t:MISTRAL_MUL27X27 %% t:* %D + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:MISTRAL_MUL27X27 +select -assert-none t:MISTRAL_MUL27X27 %% t:* %D diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys new file mode 100644 index 000000000..8dd09458e --- /dev/null +++ b/tests/techmap/bug2183.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module foo(inout a, b); + assign a = b; +endmodule +module bar(output c); + foo f(c, 1'b0); +endmodule +EOT + +hierarchy -auto-top +flatten diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v index 85318562f..3bfff4acd 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.v @@ -23,6 +23,22 @@ module top; end endfunction + function automatic [31:0] operation3; + input [4:0] rounds; + input integer num; + reg [4:0] rounds; + integer i; + begin + begin : shadow + integer rounds; + rounds = 0; + end + for (i = 0; i < rounds; i = i + 1) + num = num * 2; + operation3 = num; + end + endfunction + wire [31:0] a; assign a = 2; @@ -34,11 +50,15 @@ module top; wire [31:0] x2; assign x2 = operation2(A, a); + wire [31:0] x3; + assign x3 = operation3(A, a); + // `define VERIFY `ifdef VERIFY assert property (a == 2); assert property (A == 3); assert property (x1 == 16); assert property (x2 == 4); + assert property (x3 == 16); `endif endmodule |