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-rw-r--r--Makefile6
-rw-r--r--frontends/ast/simplify.cc4
-rw-r--r--frontends/verilog/verilog_parser.y42
-rw-r--r--techlibs/ecp5/synth_ecp5.cc13
-rw-r--r--techlibs/ice40/synth_ice40.cc24
-rw-r--r--techlibs/xilinx/synth_xilinx.cc8
-rw-r--r--tests/various/primitives.ys16
-rw-r--r--tests/various/specify.ys6
8 files changed, 85 insertions, 34 deletions
diff --git a/Makefile b/Makefile
index 47de420b8..838d29788 100644
--- a/Makefile
+++ b/Makefile
@@ -136,7 +136,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = d14acd8
+ABCREV = fd2c9b1
ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@@ -281,13 +281,13 @@ yosys.html: misc/yosys.html
else ifeq ($(CONFIG),wasi)
ifeq ($(WASI_SDK),)
-CXX = clang++
+CXX = clang
LD = clang++
AR = llvm-ar
RANLIB = llvm-ranlib
WASIFLAGS := -target wasm32-wasi --sysroot $(WASI_SYSROOT) $(WASIFLAGS)
else
-CXX = $(WASI_SDK)/bin/clang++
+CXX = $(WASI_SDK)/bin/clang
LD = $(WASI_SDK)/bin/clang++
AR = $(WASI_SDK)/bin/ar
RANLIB = $(WASI_SDK)/bin/ranlib
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 4f689fd1c..252219094 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *node = children_list[1];
if (op_type != AST_POS)
- for (size_t i = 2; i < children_list.size(); i++)
+ for (size_t i = 2; i < children_list.size(); i++) {
node = new AstNode(op_type, node, children_list[i]);
+ node->location = location;
+ }
if (invert_results)
node = new AstNode(AST_BIT_NOT, node);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 8da10df13..5d6e43330 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -885,6 +885,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
+ SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
char oper_polarity = 0;
char oper_type = oper->at(0);
@@ -973,6 +974,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = "$specrule";
+ SET_AST_NODE_LOC(cell, @1, @14);
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
cell->children.back()->str = "\\TYPE";
@@ -1099,8 +1101,8 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
} |
'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
$$ = new specify_rise_fall;
@@ -1108,11 +1110,11 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- delete $8;
- delete $10;
- delete $12;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ delete $8;
+ delete $10;
+ delete $12;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
} |
'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
$$ = new specify_rise_fall;
@@ -1120,17 +1122,17 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- delete $8;
- delete $10;
- delete $12;
- delete $14;
- delete $16;
- delete $18;
- delete $20;
- delete $22;
- delete $24;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ delete $8;
+ delete $10;
+ delete $12;
+ delete $14;
+ delete $16;
+ delete $18;
+ delete $20;
+ delete $22;
+ delete $24;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
}
specify_triple:
@@ -1747,7 +1749,9 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
- } '(' cell_port_list ')';
+ } '(' cell_port_list ')' {
+ SET_AST_NODE_LOC(astbuf2, @1, @$);
+ }
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab740ea0d..b9b236a0c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,6 +30,11 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
+ void on_register() YS_OVERRIDE
+ {
+ RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
+ }
+
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -324,6 +329,14 @@ struct SynthEcp5Pass : public ScriptPass
if (abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
+ std::string abc9_opts;
+ if (nowidelut)
+ abc9_opts += " -maxlut 4";
+ std::string k = "synth_ecp5.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
if (nowidelut)
run("abc9 -maxlut 4 -W 200");
else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9724b7dd5..2b211572d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,6 +29,13 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
+ void on_register() YS_OVERRIDE
+ {
+ RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
+ RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
+ RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
+ }
+
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -373,14 +380,15 @@ struct SynthIce40Pass : public ScriptPass
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
- int wire_delay;
- if (device_opt == "lp")
- wire_delay = 400;
- else if (device_opt == "u")
- wire_delay = 750;
- else
- wire_delay = 250;
- run(stringf("abc9 -W %d", wire_delay));
+ std::string abc9_opts;
+ std::string k = "synth_ice40.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else {
+ k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+ }
+ run("abc9 " + abc9_opts);
}
else
run("abc -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1c190d37e..229ffcb3d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,11 +619,13 @@ struct SynthXilinxPass : public ScriptPass
run("techmap " + techmap_args);
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
std::string abc9_opts;
- auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
- if (active_design->scratchpad.count(k))
+ std::string k = "synth_xilinx.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
- else
+ else {
+ k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
+ }
if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size);
if (dff_mode)
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys
new file mode 100644
index 000000000..9307ca50f
--- /dev/null
+++ b/tests/various/primitives.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input a, b, output [5:0] y);
+and (y[0], a, b);
+nand (y[1], a, b);
+or (y[2], a, b);
+nor (y[3], a, b);
+xor (y[4], a, b);
+xnor (y[5], a, b);
+endmodule
+EOT
+select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 9d55b8eb5..d7260d524 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -4,10 +4,16 @@ cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
+select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
+select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
+select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
cd test2
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
+select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
+ # ^^ Note use of macro
+select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
cd
write_verilog specify.out
design -stash gold
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 03:13:46 +0000