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-rw-r--r--backends/verilog/verilog_backend.cc22
-rw-r--r--techlibs/common/simcells.v111
-rw-r--r--techlibs/common/simlib.v18
-rw-r--r--tests/simple/dff_init.v42
-rwxr-xr-xtests/simple_defparam/run-test.sh21
-rwxr-xr-xtests/tools/autotest.sh6
6 files changed, 171 insertions, 49 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 60668f1f0..4b5a13941 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
}
}
-void dump_reg_init(std::ostream &f, SigSpec sig)
+void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
{
Const initval;
bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
}
if (gotinit) {
- f << " = ";
+ if (write_equals) f << " = ";
dump_const(f, initval);
}
}
@@ -1250,7 +1250,14 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_attributes(f, indent, cell->attributes);
f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
- if (!defparam && cell->parameters.size() > 0) {
+ std::string init;
+ if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+ std::stringstream ss;
+ dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
+ init = ss.str();
+ }
+
+ if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
f << stringf(" #(");
for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
if (it != cell->parameters.begin())
@@ -1260,6 +1267,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
dump_const(f, it->second, -1, 0, false, is_signed);
f << stringf(")");
}
+ if (!init.empty()) {
+ if (!cell->parameters.empty())
+ f << stringf(",");
+ f << stringf("\n%s .INIT(%s)", indent.c_str(), init.c_str());
+ }
f << stringf("\n%s" ")", indent.c_str());
}
@@ -1301,13 +1313,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
f << stringf("\n%s" ");\n", indent.c_str());
- if (defparam && cell->parameters.size() > 0) {
+ if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
dump_const(f, it->second, -1, 0, false, is_signed);
f << stringf(";\n");
}
+ if (!init.empty())
+ f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
}
}
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 289673e82..b9957bd5e 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -451,8 +451,9 @@ endmodule
//- 1 1 | y
//-
module \$_SR_NN_ (S, R, Q);
+parameter INIT = 1'bx;
input S, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -475,8 +476,9 @@ endmodule
//- 1 0 | y
//-
module \$_SR_NP_ (S, R, Q);
+parameter INIT = 1'bx;
input S, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -499,8 +501,9 @@ endmodule
//- 0 1 | y
//-
module \$_SR_PN_ (S, R, Q);
+parameter INIT = 1'bx;
input S, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -523,8 +526,9 @@ endmodule
//- 0 0 | y
//-
module \$_SR_PP_ (S, R, Q);
+parameter INIT = 1'bx;
input S, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -542,8 +546,9 @@ endmodule
//- type is usually only used in netlists for formal verification.)
//-
module \$_FF_ (D, Q);
+parameter INIT = 1'bx;
input D;
-output reg Q;
+output reg Q = INIT;
always @($global_clock) begin
Q <= D;
end
@@ -562,8 +567,9 @@ endmodule
//- - - | q
//-
module \$_DFF_N_ (D, C, Q);
+parameter INIT = 1'bx;
input D, C;
-output reg Q;
+output reg Q = INIT;
always @(negedge C) begin
Q <= D;
end
@@ -581,8 +587,9 @@ endmodule
//- - - | q
//-
module \$_DFF_P_ (D, C, Q);
+parameter INIT = 1'bx;
input D, C;
-output reg Q;
+output reg Q = INIT;
always @(posedge C) begin
Q <= D;
end
@@ -600,8 +607,9 @@ endmodule
//- - - - | q
//-
module \$_DFFE_NN_ (D, C, E, Q);
+parameter INIT = 1'bx;
input D, C, E;
-output reg Q;
+output reg Q = INIT;
always @(negedge C) begin
if (!E) Q <= D;
end
@@ -619,8 +627,9 @@ endmodule
//- - - - | q
//-
module \$_DFFE_NP_ (D, C, E, Q);
+parameter INIT = 1'bx;
input D, C, E;
-output reg Q;
+output reg Q = INIT;
always @(negedge C) begin
if (E) Q <= D;
end
@@ -638,8 +647,9 @@ endmodule
//- - - - | q
//-
module \$_DFFE_PN_ (D, C, E, Q);
+parameter INIT = 1'bx;
input D, C, E;
-output reg Q;
+output reg Q = INIT;
always @(posedge C) begin
if (!E) Q <= D;
end
@@ -657,8 +667,9 @@ endmodule
//- - - - | q
//-
module \$_DFFE_PP_ (D, C, E, Q);
+parameter INIT = 1'bx;
input D, C, E;
-output reg Q;
+output reg Q = INIT;
always @(posedge C) begin
if (E) Q <= D;
end
@@ -677,8 +688,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_NN0_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
@@ -700,8 +712,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_NN1_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
@@ -723,8 +736,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_NP0_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
@@ -746,8 +760,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_NP1_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
@@ -769,8 +784,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_PN0_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
@@ -792,8 +808,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_PN1_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
@@ -815,8 +832,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_PP0_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
@@ -838,8 +856,9 @@ endmodule
//- - - - | q
//-
module \$_DFF_PP1_ (D, C, R, Q);
+parameter INIT = 1'bx;
input D, C, R;
-output reg Q;
+output reg Q = INIT;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
@@ -862,8 +881,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_NNN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(negedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -889,8 +909,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_NNP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(negedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -916,8 +937,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_NPN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(negedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -942,8 +964,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_NPP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(negedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -968,8 +991,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_PNN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(posedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -995,8 +1019,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_PNP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(posedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -1022,8 +1047,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_PPN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(posedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
@@ -1048,8 +1074,9 @@ endmodule
//- - - - - | q
//-
module \$_DFFSR_PPP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @(posedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
@@ -1072,8 +1099,9 @@ endmodule
//- - - | q
//-
module \$_DLATCH_N_ (E, D, Q);
+parameter INIT = 1'bx;
input E, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (E == 0)
Q <= D;
@@ -1092,8 +1120,9 @@ endmodule
//- - - | q
//-
module \$_DLATCH_P_ (E, D, Q);
+parameter INIT = 1'bx;
input E, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (E == 1)
Q <= D;
@@ -1114,8 +1143,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 0)
Q <= 0;
@@ -1141,8 +1171,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 1)
Q <= 0;
@@ -1168,8 +1199,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 0)
Q <= 0;
@@ -1194,8 +1226,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 1)
Q <= 0;
@@ -1220,8 +1253,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 0)
Q <= 0;
@@ -1247,8 +1281,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 1)
Q <= 0;
@@ -1274,8 +1309,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 0)
Q <= 0;
@@ -1300,8 +1336,9 @@ endmodule
//- - - - - | q
//-
module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
always @* begin
if (R == 1)
Q <= 0;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..a1e0c1575 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,10 +1464,11 @@ module \$dff (CLK, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK;
input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
@@ -1483,10 +1484,11 @@ module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK, EN;
input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY;
always @(posedge pos_clk) begin
@@ -1504,10 +1506,11 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK;
input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@@ -1537,10 +1540,11 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK, ARST;
input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
wire pos_clk = CLK == CLK_POLARITY;
wire pos_arst = ARST == ARST_POLARITY;
@@ -1559,10 +1563,11 @@ module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input EN;
input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
always @* begin
if (EN == EN_POLARITY)
@@ -1580,10 +1585,11 @@ parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input EN;
input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
wire pos_en = EN == EN_POLARITY;
wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 000000000..be947042e
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,42 @@
+module dff0_test(n1, n1_inv, clk);
+ input clk;
+ output n1;
+ reg n1 = 32'd0;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff1_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd1 *)
+ output n1;
+ reg n1 = 32'd1;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd0 *) // Must be consistent with reg initialiser below
+ output n1;
+ reg n1 = 32'd0;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd1 *) // Must be consistent with reg initialiser below
+ output n1;
+ reg n1 = 32'd1;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
new file mode 100755
index 000000000..137e15076
--- /dev/null
+++ b/tests/simple_defparam/run-test.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+OPTIND=1
+seed="" # default to no seed specified
+while getopts "S:" opt
+do
+ case "$opt" in
+ S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+ seed="SEED=$arg" ;;
+ esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+ echo "$0: Error: Icarus Verilog 'iverilog' not found."
+ exit 1
+fi
+
+cp ../simple/*.v .
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 218edf931..6fdd1e80a 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -28,7 +28,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
fi
-while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
case "$opt" in
x)
use_xsim=true ;;
@@ -65,6 +65,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
include_opts="$include_opts -I $OPTARG"
xinclude_opts="$xinclude_opts -i $OPTARG"
minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+ B)
+ backend_opts="$backend_opts $OPTARG" ;;
-)
case "${OPTARG}" in
xfirrtl)
@@ -82,7 +84,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
;;
esac;;
*)
- echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
+ echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
exit 1
esac
done
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-16 15:24:16 +0000