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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-08-30 10:29:47 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-30 10:29:47 +0300 |
| commit | f23b540b45fb485e38cb0a86e67cddb11dbd2a20 (patch) | |
| tree | e204a8a77536b54b36517fab2b7d38ce46168cf7 /tests | |
| parent | d144748401df3f6d527771e6d30cc1eb1e08734e (diff) | |
| parent | 694e30a35426b9582a1f2db730528d4d34305795 (diff) | |
| download | yosys-f23b540b45fb485e38cb0a86e67cddb11dbd2a20.tar.gz yosys-f23b540b45fb485e38cb0a86e67cddb11dbd2a20.tar.bz2 yosys-f23b540b45fb485e38cb0a86e67cddb11dbd2a20.zip | |
Merge branch 'master' into master
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/ice40_opt.ys | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys new file mode 100644 index 000000000..b17c69c91 --- /dev/null +++ b/tests/ice40/ice40_opt.ys @@ -0,0 +1,26 @@ +read_verilog -icells -formal <<EOT +module top(input CI, I0, output [1:0] CO, output O); + wire A = 1'b0, B = 1'b0; + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(~16'b 0110_1001_1001_0110) + ) u0 ( + .A(A), + .B(B), + .CI(CI), + .I0(I0), + .I3(CI), + .CO(CO[0]), + .O(O) + ); + SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1])); +endmodule +EOT + +equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt +design -load postopt +select -assert-count 1 t:* +select -assert-count 1 t:$lut |