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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 14:21:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 14:21:15 +0100 |
| commit | e9368a1d7e13bc691f86f25cd80981110b937cab (patch) | |
| tree | b3dd1332d669c288d45c52595607ff6b2f364a48 /tests | |
| parent | dcf2e242406d563254013ea7db4b29b55be96eff (diff) | |
| download | yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.tar.gz yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.tar.bz2 yosys-e9368a1d7e13bc691f86f25cd80981110b937cab.zip | |
Various fixes for memories with offsets
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/memory.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 23e93ac91..67f89cd75 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -213,7 +213,7 @@ module memtest09 ( input a_wen, b_wen, output reg [3:0] a_dout, b_dout ); - reg [3:0] memory [0:35]; + reg [3:0] memory [10:35]; always @(posedge clk) begin if (a_wen) @@ -222,7 +222,7 @@ module memtest09 ( end always @(posedge clk) begin - if (b_wen && (10 + a_addr != 20 + b_addr)) + if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen)) memory[20 + b_addr] <= b_din; b_dout <= memory[20 + b_addr]; end |