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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-04 16:30:24 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-04 16:30:24 +0200 |
| commit | e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22 (patch) | |
| tree | f92ae3922768bccd01aa159c85638d6b868e7945 /tests | |
| parent | c39ebe6ae0e41cf9a84da852fa3cf9f71937a9b2 (diff) | |
| download | yosys-e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22.tar.gz yosys-e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22.tar.bz2 yosys-e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22.zip | |
peepopt.muldiv: Add a signedness check.
Fixes #2318.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug2318.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/opt/bug2318.ys b/tests/opt/bug2318.ys new file mode 100644 index 000000000..9de6f88ec --- /dev/null +++ b/tests/opt/bug2318.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module t(input [3:0] A, input [3:0] B, output signed [3:0] Y); + +wire [7:0] P = A * B; +wire signed [7:0] SP = P; +wire signed [3:0] SB = B; +assign Y = SP / SB; + +endmodule +EOT + +equiv_opt -assert peepopt |