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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 22:48:23 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-06 22:48:23 -0700 |
| commit | e2c2d784c8217e4bcf29fb6b156b6a8285036b80 (patch) | |
| tree | ebe87df4dd1c53a450c9b4b08c53e1eabf5f626a /tests | |
| parent | 51b559af2cc60226d85880efc3705f0860ffaed6 (diff) | |
| download | yosys-e2c2d784c8217e4bcf29fb6b156b6a8285036b80.tar.gz yosys-e2c2d784c8217e4bcf29fb6b156b6a8285036b80.tar.bz2 yosys-e2c2d784c8217e4bcf29fb6b156b6a8285036b80.zip | |
Make one check $shift(x)? only; change testcase to be 8b
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/peepopt.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index a476133a2..dcf3cacbd 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <<EOT module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); -assign y = 1'b1 >> (w * (3'b110)); +assign y = 1'b1 >> (w * (8'b110)); endmodule EOT @@ -25,7 +25,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 1 t:$mul +select -assert-count 0 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### |