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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:18:48 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-26 12:18:48 -0800 |
commit | dfb23a79dd0e2ffbe4f058eadb552d8194540eef (patch) | |
tree | 5feb82b3cfea50c0583f63b0e2fd25db6af0aab6 /tests | |
parent | 7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2 (diff) | |
download | yosys-dfb23a79dd0e2ffbe4f058eadb552d8194540eef.tar.gz yosys-dfb23a79dd0e2ffbe4f058eadb552d8194540eef.tar.bz2 yosys-dfb23a79dd0e2ffbe4f058eadb552d8194540eef.zip |
Uncomment out more tests
Diffstat (limited to 'tests')
-rw-r--r-- | tests/simple_abc9/abc9.v | 64 |
1 files changed, 39 insertions, 25 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 8a809e480..eca340693 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -63,30 +63,44 @@ always @(io or oe) assign io = oe ? ~latch : 8'bz; endmodule -// TODO -//module abc9_test011(inout [7:0] io, input oe); -//reg [7:0] latch; -//always @(io or oe) -// if (!oe) -// latch[3:0] <= io; -// else -// latch[7:4] <= io; -//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; -//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; -//endmodule - -// TODO -//module abc9_test012(inout [7:0] io, input oe); -//abc9_test012_sub sub(io, oe); -//endmodule -// -//module abc9_test012_sub(inout [7:0] io, input oe); -//reg [7:0] latch; +module abc9_test011(inout io, input oe); +reg latch; +always @(io or oe) + if (!oe) + latch <= io; +//assign io = oe ? ~latch : 8'bz; +endmodule + +module abc9_test012(inout io, input oe); +reg latch; //always @(io or oe) // if (!oe) -// latch[3:0] <= io; -// else -// latch[7:4] <= io; -//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; -//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; -//endmodule +// latch <= io; +assign io = oe ? ~latch : 8'bz; +endmodule + +module abc9_test013(inout [3:0] io, input oe); +reg [3:0] latch; +always @(io or oe) + if (!oe) + latch[3:0] <= io[3:0]; + else + latch[7:4] <= io; +assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +endmodule + +module abc9_test014(inout [7:0] io, input oe); +abc9_test012_sub sub(io, oe); +endmodule + +module abc9_test012_sub(inout [7:0] io, input oe); +reg [7:0] latch; +always @(io or oe) + if (!oe) + latch[3:0] <= io; + else + latch[7:4] <= io; +assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +endmodule |