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| author | Maciej Dudek <mdudek@antmicro.com> | 2021-07-29 21:10:02 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-30 16:17:22 +0200 |
| commit | cfddef5d7d265d2260aad2d6ea8595f8b660eb6a (patch) | |
| tree | 09b9f1983c37497f7d96060f91990ad062e7934a /tests | |
| parent | c016f6a4236fb970196f35c2afb0f2c7c237a77f (diff) | |
| download | yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.tar.gz yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.tar.bz2 yosys-cfddef5d7d265d2260aad2d6ea8595f8b660eb6a.zip | |
Fixes xc7 BRAM36s
UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode.
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions