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| author | Jannis Harder <me@jix.one> | 2023-01-30 16:14:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-30 16:14:24 +0100 |
| commit | c235802f4acf85b04c175a6b643aed17dd4c6f8c (patch) | |
| tree | fdef94bb6219fec593acaf4b4ec2b75edc291805 /tests | |
| parent | 419f91a2b99fbd1b61b09682947dbb782c19a97d (diff) | |
| parent | b08a8807044980b7906362848f62291ede50e696 (diff) | |
| download | yosys-c235802f4acf85b04c175a6b643aed17dd4c6f8c.tar.gz yosys-c235802f4acf85b04c175a6b643aed17dd4c6f8c.tar.bz2 yosys-c235802f4acf85b04c175a6b643aed17dd4c6f8c.zip | |
Merge pull request #3650 from jix/rtlil_roundtrip_z_bits
backends/rtlil: Do not shorten a value with z bits to 'x
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/rtlil_z_bits.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/rtlil_z_bits.ys b/tests/various/rtlil_z_bits.ys new file mode 100644 index 000000000..c38669159 --- /dev/null +++ b/tests/various/rtlil_z_bits.ys @@ -0,0 +1,9 @@ +! mkdir -p temp +read_rtlil <<EOT +module \test + wire output 1 \a + connect \a 1'z +end +EOT +write_rtlil temp/rtlil_z_bits.il +! grep -F -q "connect \\a 1'z" temp/rtlil_z_bits.il |