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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 16:11:14 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 16:11:39 -0700 |
commit | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (patch) | |
tree | fe44f2a947768d15d88e44c149a762bd75d9e2b8 /tests | |
parent | d9c915042a610672e313f976cdbcbf9a814c380d (diff) | |
download | yosys-ac2aff9e28a087a9a2697cd6ccf754af738903a7.tar.gz yosys-ac2aff9e28a087a9a2697cd6ccf754af738903a7.tar.bz2 yosys-ac2aff9e28a087a9a2697cd6ccf754af738903a7.zip |
Fix abc9 with (* keep *) wires
Diffstat (limited to 'tests')
-rw-r--r-- | tests/simple_abc9/abc9.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index eca340693..f37d975ff 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -104,3 +104,41 @@ always @(io or oe) assign io[3:0] = oe ? ~latch[3:0] : 4'bz; assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; endmodule + +module abc9_test015(input a, output b, input c); +assign b = ~a; +(* keep *) wire d; +assign d = ~c; +endmodule + +module abc9_test016(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c <= ~a; +endmodule + +module abc9_test017(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c = b; +endmodule + +module abc9_test018(input a, output b, output c); +assign b = ~a; +(* keep *) wire [1:0] d; +assign c = &d; +endmodule + +module abc9_test019(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +reg d; +always @* d <= &c; +endmodule + +module abc9_test020(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +(* keep *) reg d; +always @* d <= &c; +endmodule |