Merge https://github.com/cliffordwolf/yosys

1 files changed, 21 insertions, 0 deletions

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index d58ed9d1a..9fddce26c 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -243,3 +243,24 @@ module memtest10(input clk, input [5:0] din, output [5:0] dout);
 
 	assign dout = queue[3];
 endmodule
+
+// ----------------------------------------------------------
+
+module memtest11(clk, wen, waddr, raddr, wdata, rdata);
+	input clk, wen;
+	input [1:0] waddr, raddr;
+	input [7:0] wdata;
+	output [7:0] rdata;
+
+	reg [7:0] mem [3:0];
+
+	assign rdata = mem[raddr];
+
+	always @(posedge clk) begin
+		if (wen)
+			mem[waddr] <= wdata;
+		else
+			mem[waddr] <= mem[waddr];
+	end
+endmodule
+