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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:36:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:36:01 -0700 |
| commit | a6776ee35ee5404ca7d5b63fd2daccc46354112c (patch) | |
| tree | 2925a1aa432fcb6cdb78037a9cf72dd2b803c4bd /tests | |
| parent | 7d8db1c0538552d1893849ff8c9c60b2025ec267 (diff) | |
| download | yosys-a6776ee35ee5404ca7d5b63fd2daccc46354112c.tar.gz yosys-a6776ee35ee5404ca7d5b63fd2daccc46354112c.tar.bz2 yosys-a6776ee35ee5404ca7d5b63fd2daccc46354112c.zip | |
mem2reg to preserve user attributes and src
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/mem2reg.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys new file mode 100644 index 000000000..00389c700 --- /dev/null +++ b/tests/various/mem2reg.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT +module top; +parameter DATADEPTH=2; +parameter DATAWIDTH=1; +(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0]; +(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0]; +endmodule +EOT + +proc +cd top +select -assert-count 1 m:data1 a:src=<<EOT:4 %i +select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i |