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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 14:17:03 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 14:17:03 +0300 |
| commit | 94a56c14b78a2872d65bb30371151e934a259275 (patch) | |
| tree | 230165279a94f28e70f7a9841f4364ce27d47cbc /tests | |
| parent | f4a48ce8e6785fe9828b8896b9a60a74580dc2eb (diff) | |
| download | yosys-94a56c14b78a2872d65bb30371151e934a259275.tar.gz yosys-94a56c14b78a2872d65bb30371151e934a259275.tar.bz2 yosys-94a56c14b78a2872d65bb30371151e934a259275.zip | |
div_mod test fix
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index f55490572..21cac7144 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -5,5 +5,5 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 62 t:SB_LUT4 -select -assert-count 65 t:SB_CARRY +select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |