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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-01-28 18:26:10 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-01-28 18:26:10 +0100 |
| commit | 94191a93ddf85f8849d40e5ee85fd659b0780994 (patch) | |
| tree | 9791158b6df75124da265567e1d2b72b21655c18 /tests | |
| parent | 49c9b63e0fc45d550afa089eff8fb92b6dce88b7 (diff) | |
| download | yosys-94191a93ddf85f8849d40e5ee85fd659b0780994.tar.gz yosys-94191a93ddf85f8849d40e5ee85fd659b0780994.tar.bz2 yosys-94191a93ddf85f8849d40e5ee85fd659b0780994.zip | |
Updated test to use assert-max
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/efinix/mux.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index 91c110ae0..a5ab80d8b 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -36,6 +36,6 @@ proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 11 t:EFX_LUT4 +select -assert-max 12 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D |