aboutsummaryrefslogtreecommitdiffstats
path: root/tests
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2016-05-20 16:48:50 +0200
committerClifford Wolf <clifford@clifford.at>2016-05-20 16:48:50 +0200
commit884ec967871dede8d5ad6fb730a405e421a18dbe (patch)
treed08e665b213e18f0658c85cd19d4b3e27272e19b /tests
parentf3983a094052e875e05823a6063c1775d1f84b39 (diff)
parent8c3bc2ac0da4457f90775608e9701e0a7ba1e4cf (diff)
downloadyosys-884ec967871dede8d5ad6fb730a405e421a18dbe.tar.gz
yosys-884ec967871dede8d5ad6fb730a405e421a18dbe.tar.bz2
yosys-884ec967871dede8d5ad6fb730a405e421a18dbe.zip
Merge branch 'master' of https://github.com/Kmanfi/yosys
Diffstat (limited to 'tests')
-rwxr-xr-xtests/tools/autotest.sh8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 840cb19ff..feaadb1a1 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -65,8 +65,8 @@ compile_and_run() {
if $use_modelsim; then
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
/opt/altera/$altver/modelsim_ase/bin/vlib work
- /opt/altera/$altver/modelsim_ase/bin/vlog "$@"
- /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output"
+ /opt/altera/$altver/modelsim_ase/bin/vlog +define+dmp_name=\"$output\" "$@"
+ /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
elif $use_xsim; then
(
set +x
@@ -76,8 +76,8 @@ compile_and_run() {
/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output"
)
else
- iverilog -s testbench -o "$exe" "$@"
- vvp -n "$exe" > "$output"
+ iverilog -Ddmp_name=\"$output\" -s testbench -o "$exe" "$@"
+ vvp -n "$exe"
fi
}