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author | Clifford Wolf <clifford@clifford.at> | 2016-06-17 20:15:11 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-06-17 20:15:11 +0200 |
commit | 7a4ee5da747382df323d41f60e974ef92bdc1e82 (patch) | |
tree | 99713e0311c18e587eb6a1a7fd1d83a498172331 /tests | |
parent | f498204ae462e2307f93c3ba8e6ba3b793b94d1f (diff) | |
download | yosys-7a4ee5da747382df323d41f60e974ef92bdc1e82.tar.gz yosys-7a4ee5da747382df323d41f60e974ef92bdc1e82.tar.bz2 yosys-7a4ee5da747382df323d41f60e974ef92bdc1e82.zip |
Fixed init issue in mem2reg_test2 test case
Diffstat (limited to 'tests')
-rw-r--r-- | tests/simple/mem2reg.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 40f490b75..b1ab04d62 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -19,9 +19,9 @@ endmodule // ------------------------------------------------------ -module mem2reg_test2(clk, mode, addr, data); +module mem2reg_test2(clk, reset, mode, addr, data); -input clk, mode; +input clk, reset, mode; input [2:0] addr; output [3:0] data; @@ -33,6 +33,10 @@ assign data = mem[addr]; integer i; always @(posedge clk) begin + if (reset) begin + for (i=0; i<8; i=i+1) + mem[i] <= i; + end else if (mode) begin for (i=0; i<8; i=i+1) mem[i] <= mem[i]+1; |