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author | Clifford Wolf <clifford@clifford.at> | 2019-08-28 00:18:14 +0200 |
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committer | GitHub <noreply@github.com> | 2019-08-28 00:18:14 +0200 |
commit | 70c0cddb1eac1165cb78f1f4eb1d149792dcc95a (patch) | |
tree | 0ff420f1b100c4069fc9f6dc1ed1e1409afd4b12 /tests | |
parent | d361f5ab795f5b823a594f1fee75f93a78995481 (diff) | |
parent | 28133432bea4a3fa01cd2f5e82a52a853cfccb84 (diff) | |
download | yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.tar.gz yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.tar.bz2 yosys-70c0cddb1eac1165cb78f1f4eb1d149792dcc95a.zip |
Merge pull request #1325 from YosysHQ/eddie/sat_init
In sat: 'x' in init attr should be ignored
Diffstat (limited to 'tests')
-rw-r--r-- | tests/sat/initval.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; + always @* + asdf[2:0] = 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule |